TimeVision is an automated and proven design constraint development and verification platform to manage large system-on-chip designs above 100+ million instances and allows SoC and IP developers to reach unmatched productivity gains across the design flow and reduce costs.

Silicon design is becoming vastly more complicated and costly, and harder to design and verify. Today s SoCs exploding complexity is driven by raw design size, increasing use of IP blocks, advanced technology node, generating numerous number of clocks and clocked domains, and complexity of constraints to close timing across all combinations of corners and modes. There is a demand for a comprehensive product to generate and validate design constraints that correlate with STA engines to ensure design correctness.

The huge cost of an error in constraints, clocking or timing often forces design teams to adopt a minimization strategy, designing a completely minimal, safe set of timing constraints that are the least prone to error. Experienced leaders in the silicon design field recognize this as a complex, multi-faceted problem that requires a variety of capabilities and techniques. Simple structural or semantic tools and approaches will only catch simple problems while emitting copious numbers of false-positive errors requiring designer review. The solution should aid in the goal of helping the design team create design constraints that cover the requirements of the design, allowing it to meet its power, performance and area goals while minimizing the risk of a respin due to a clocking or timing issue.

Using multi-core software architecture and innovative formal verification technology, Ausdia founders created TimeVision to generate and validate design constraints that correlate with STA engines to ensure design correctness and consistency from RTL to GDSII.