Arteris provides Network-on-Chip (NoC) interconnect IP to improve performance, power consumption and die size of system-on-chip (SoC) devices for consumer electronics, mobile, automotive and other applications.
Using Arteris solves pain for our customers. Traditional bus and crossbar interconnect approaches create serious problems for architects, digital and physical designers, and integrators: Massive numbers of wires, increased heat and power consumption, failed timing closure, spaghetti-like routing congestion leading to increased die area, and difficulty making changes for derivatives.
Whether you are using AXI, OCP, AHB or a proprietary protocol, Arteris Network-on-Chip (NoC) IP reduces the number of wires by nearly one half, resulting in fewer gates and a more compact chip floor plan. Having the option to configure each connection’s width, and each transaction’s dynamic priority, assures meeting latency and bandwidth requirements. And with the Arteris IP configuration tool suite, design and verification can be done easily, in a matter of days or even hours.
Arteris invented Network-on-Chip technology, offering the world’s first commercial solution in 2006. Arteris connects the IP blocks in semiconductors from Qualcomm, Samsung, TI, and others, representing over 50 system-on-chip devices. Find out more about Arteris products.