D&R News Alert
April 3rd, 2025
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Welcome to the issue of April 3rd, 2025 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

Foundry and Technogy News
■ GlobalFoundries and UMC Mull Potential Merger
Live Webinar: Verifying AI Designs - Solving the Challenge of Quadrillions of Verification Cycles
Synopsys

When: Wednesday, April 9th | 10:00 a.m. – 11:00 a.m. PDT
Speaker: Frank Schirrmeister, Executive Director, Strategic Programs, System Solutions, Synopsys

Register here >>

Design and Verification Platforms
■ Exploring the Rationale for HAV in Complex SoCs
■ ProMOS Adopts Silvaco Victory TCAD Solution for the Development of Next-Gen Silicon Photonics Devices
Memory IP
■ GUC Announces Tape-Out of the World's First HBM4 IP on TSMC N3P
Design Partner of the Week
IP Core Worx
IP Core Worx’ robust and dependable IP suite
• Wireless Communication and FEC
• DVB and Digital signal processing
• Custom designed cores
Learn more >>

Interface IP
■ Silicon-Proven MIPI CSI-2 & DSI-2 Tx/Rx IP Cores for your Camera & Display SoCs
■ TeraSignal to Showcase Retimer-Less PCIe 6.0 over Optics Featuring Synopsys IP at OFC 2025
RISC-V
■ RISC-V in 2025: Progress, Challenges,and What's Next for Automotive & OpenHardware - By Keysom
Artificial Intelligence
■ VeriSilicon Launches ISP9000: The Next-Generation AI-Embedded ISP for Intelligent Vision Applications
■ Frontgrade Gaisler Launches New GRAIN Line and Wins SNSA Contract to Commercialize First Energy-Efficient Neuromorphic AI for Space Applications
■ Fraunhofer IIS Walks the Line for Edge AI
■ BrainChip Partners with RTX’s Raytheon for AFRL Radar Contract
Rambus
Implementing State-of-the-Art Digital Protection with Rambus CryptoManager Security IP

• Live webinar on April 16th exploring a customizable three-tiered Root of Trust security architecture for processors and SoCs
• Learn how to safeguard your chip designs against cyber attacks and side-channel exploits
• Learn about the new Rambus CryptoManager Hub and Core solution
• Live Q&A with Rambus Security Expert, Parvez Shaik

Register Today >>

Security Solutions
■ What tamper detection IP brings to SoC designs - by Agile Analog
Space Solutions
■ Movellus and RTX's SEAKR Engineering Collaborate on Advancing Mission-Critical ASICs
■ QuickLogic Announces $1.4 Million Incremental Funding Modification for its Strategic Radiation Hardened Program
 
biOdTe / Gemini: IP cores for Network Data Diodes
CetraC

• Support UDP, TCP and industrial protocols
• Multiple Speed : 10Gbs or 1Gbs
• One Way, address translation and protocol breaker
• 100% hardware for all targets as FPGA & ASIC
Learn more >>

 
Audio/Video
■ Latest intoPIX JPEG XS Codec Powers FOR-A's FA-1616 for Efficient IP Production at NAB 2025
■ The Critical Factors of a High-performance Audio Codec. What Chip Designers Need to Know - By Innosilicon
■ Village Island Enhances its AI100 with intoPIX's JPEG XS Technology for Advanced Real-Time Analysis
Automotive
■ Digital Core Design Unveils DPSI5 - The Next-Generation IP Core for PSI5 Communication
■ SEALSQ and IC'ALPS Join Forces to Advance Post-Quantum Secure ASICs for Automotive Functional Safety
Quantum computing
■ New cryostatic systems elevate current research on Qubits
Green Electronics
■ Recycling Critical Materials from E-Waste for a Circular Economy - by 3DS
Partner News
■ Arteris Opens New Engineering Hub in Poland
Business News
■ TSMC opens up 2nm wafer fab, races to mass production






Synopsys LPDDR Controller for LPDDR5X, LPDDR5 and LPDDR4X
• Complete, integrated LPDDR5X/5/4X solution...
• Supports LPDDR5X, LPDDR5 and LPDDR4X protocols

New IP
• AV1/HEVC/AVC/VP9 Video Codec HW IP 8K30fps@550MHz by Chips&Media
• Low Noise, High PSRR Replica Voltage Regulator by Weasic Microelectronics
• LPDDR Controller for LPDDR5X, LPDDR5 and LPDDR4X by Synopsys
• KYBER IP Core by ElectraIC
• High-efficiency vector DSP cores for 5G and 5G-Advanced by Ceva

What they said at
IP SoC EU 24

6R Greenness Profiling for IC and Boards
Gabrièle Saucier, CEO, Design And Reuse

Strategic decision-making in the semiconductor sector: shifting from relative to absolute sustainability
Thibault Pirson, PhD, research assistant, UCLouvain

Standardizing CDC and RDC abstract models
Jean-Christophe Brignone, SMTS, STMicroelectronics

Make Chip: the one and only turnkey 22FDX design environment
Patrick Döll, Physical IC Design Engineer, Racyics GmbH

Keysom Studio - Design Space Exploration of processor architectures
Luca TESTA, Cofounder & COO, Keysom

Standard EDA tools based asynchronous design flow
GODARD Adrien, PhD student, STMicroelectronics

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