D&R News Alert
March 24th, 2025
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Welcome to the issue of March 24th, 2025 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

Rambus
Customizable three tier Root of Trust security architecture for processors or SoCs

• For data center, highly secure applications and automotive
• Flexible and configurable family of accelerator cores to best suit your application needs
• Safeguard your device from malware and tamper attacks with the Rambus CryptoManager Root of Trust
Learn more >>

Foundry and Technology News
■ Japan’s Rapidus Preps 2nm Foundry Process And Chiplets
■ FAMES Pilot Line Launches Open-Access Call for Chip Industry
■ Soitec contributes to accelerated development of integrated optical connectivity solutions for AI datacentres with its silicon photonics SOI technology
What's new in FD-SOI?
About Standards
■ Accellera Announces IEEE Standard 1801™-2024 is Available Through IEEE GET Program
Memory Interface
■ Brite Semiconductor Releases DDR3/4, LPDDR3/4 Combo IP
Design Platform
■ Synopsys: Autonomous AI Agents to Tame Chip Design Complexity
■ Siemens Xcelerator: Siemens accelerates IT and OT integration with Microsoft for Edge, Cloud, AI and Simulation
Vayavya Labs
Accident Scenario Libraries

• Simulating real-world crash scenarios from reported accidents
• Automated scenario generation from accident databases
• Standardized OpenSCENARIO® for verification & validation

Click here to explore our solutions! >>

Analog IP
■ Omni Design Technologies Delivers Multi-Gigahertz SWIFT™ Data Converter Solutions for Satellite Communications
RISC-V
■ Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
Artificial Intelligence
■ SoCs Get a Helping Hand from AI Platform FlexGen
■ Dnotitia and HyperAccel Collaborate to Develop Optimized AI Inference System for RAG
Automotive
■ Impact Rating And Attack Feasibility In Automotive Cybersecurity - by Vayavya Labs
eFPGA
■ Zero ASIC launches world's first open standard eFPGA product
Green Electronics

Products
 SUSTAIN-E (SUmmer School on susTAINable Electronics)
June 16-20, 2025 - Grenoble, France
• Learn more about green electronics... >>

Partner News
■ World-Leading’ Semiconductor Design Centre Will ‘Strengthen Wales’ Leadership in Chip Design’
■ Vayavya Labs At The ADAS Show 2025
■ QuickLogic Announces the Amendment and Extension of Credit Facility
Business News
■ SoftBank Group to Acquire Ampere Computing
■ Global Top 10 IC Design Houses See 49% YoY Growth in 2024, NVIDIA Commands Half the Market, Says TrendForce
Do not miss IP-SoC
Silicon Valley 2025
Opens on April 24th, 2025 		Program Available >>
Register Now >>








Synopsys PCIe 4.0 PHY IP for SS 14LPU
• Physical Coding Sublayer (PCS) block with PIPE interface
• Support PCIe 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization

New IP
• TSMC FPD-Link / OpenLDI / LVDS forwarded clock SERDES Link by Silicon Creations
• On-Chip IO to Core Voltage Buck Regulator by Obsidian Technology
• SerDes Hard Macro-IP in GlobalFoundries 22FDX by Global IP Core Sales
• LPDDR5 IP - High performance and low power by KNiulink Semiconductor

What they said at
IP SoC EU 24

Interview with Dr. Calliope-Louisa Sotiropoulou - CAST, Inc.

Interview with Patrick Döll - Physical IC Design Engineer - Racyics GmbH

Interview with Luca TESTA - Cofounder & COO - Keysom

Interview with Ettore Antonino Giliberti - Senior Staff Application Engineer - SmartDV Technologies

Innovating the Future with SOIL: Next-Gen IPs, Transfer from Research to Silicon
Damian Panter, Fraunhofer

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