D&R News Alert
March 13th, 2025
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Welcome to the issue of March 13th, 2025 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

CEVA Ceva-XC21 and Ceva-XC23 baseband DSPs for 5G IoT/UE and 5G-Adv/Infrastructure
  • High-efficiency Ceva-XC21 DSP for low-power cellular IoT/UE modems
  • High-performance Ceva-XC23 DSP for Satcom and RAN in 5G-Adv & pre-6G
  • Scalable architecture and dual-thread design with support for AI workloads
  • 5th gen Ceva-XC vector DSP architecture compatible with enhanced 5G ISA
Learn more >>>

Interconnect IP
■ GUC Announces Successful Launch of Industry's First 32G UCIe Silicon on TSMC 3nm and CoWoS Technology
Design platform
■ Synopsys Introduces Virtualizer Native Execution on Arm Hardware to Accelerate Software-defined Product Development
Ausdia Joins TSMC Open Innovation Platform® (OIP) EDA Alliance

Ausdia • Integrating Its Time Vision platform™
• Providing full advantage of TSMC’s advanced process nodes
• Enhancing design performance and quality

 Learn More

Interface IP
■ Logic Fruit Technologies Releases High-Speed Interface IPs Stack for Advanced Computing
RISC-V
■ Codasip selected to design a high-end RISC-V processor for the EU-funded DARE project
Aeonic™ Integrated Droop Response System
Movellus

• Reduce chip-level Vmin
• Single-cycle droop detection and response
• Multi-threshold droop detection
• Droop-specific telemetry for silicon analytics engines

Learn More >>   White paper >>

Artificial Intelligence
■ Axelera AI and Kudelski IoT Partner for Next-Generation Edge Intelligent Ecosystem
■ Tenstorrent and UnsungFields Announce Strategic Technology Alliance
■ How AI Will Define the Next Silicon Supercycle
Automotive
■ Arm Kleidi Arrives in Automotive Markets to Accelerate Performance for AI-based Applications
■ Vector Informatik and Synopsys Announce Strategic Collaboration to Advance Software-Defined Vehicle Development
■ Imagination GPU Powers Renesas R-Car Gen 5 SoC
■ BOS Semiconductors Signed Development Contract for ADAS Chiplet SoC with an European OEM
■ Weebit Nano fully qualifies ReRAM module to AEC-Q100 for automotive applications
■ Dream Chip, Cadence Unveil Automotive SoC with Tensilica IP at embedded world '25 – by Cadence
Security IP
■ Rambus Enhances Data Center and AI Protection with Next-Gen CryptoManager Security IP Solutions
■ Crypto Quantique demonstrating device security platform that accelerates CRA-compliant development
■ Kudelski IoT and u-blox collaborate to bring advanced security to autonomous driving, drones and agricultural applications
■ Fifth quantum-secure encryption algorithm selected
Products
 ❖ The Critical Factors of a High-performance Audio Codec. What Chip Designers Need to Know. By Innosilicon.

Audio/Video
■ Allegro DVT Launches its First AI-Based Neural Video Processing IP
■ Allegro DVT Acquires Vicuesoft to Build a Worldwide Leader in Video Codecs Compliance and Analysis Solutions
Internet of Things
■ Qualcomm to Bolster AI and IoT Capabilities with Edge Impulse Acquisition
Partner News
■ CAST and Shikino High-Tech Partner to Expand Silicon IP Offerings and Market Reach
■ Omni Design Technologies Opens Austin Design Center
Business News
■ TSMC pitched Intel foundry JV to Nvidia, AMD and Broadcom, sources say
■ Europe’s chip market continues to shrink amidst global growth
■ Malaysia taps ARM for $250m chip boost





New IP
• 32 kHz RC low-drift oscillator in TSMC 22ULL by Dolphin Semiconductor
• MIPI D-PHY Receiver with PPI by Sunplus Technology
• LDPC Encoder / Decoder by IP-Maker
• 5 GHz 250 fs jitter Phase Locked Loop IP Block by Alphacore
• MIPI C-PHY v2.0 D-PHY v2.1 RX for GF 12LP+ by Synopsys

What they said at
IP SoC EU 24

6R Greenness Profiling for IC and Boards
Gabrièle Saucier, CEO, Design And Reuse

Strategic decision-making in the semiconductor sector: shifting from relative to absolute sustainability
Thibault Pirson, PhD, research assistant, UCLouvain

Standardizing CDC and RDC abstract models
Jean-Christophe Brignone, SMTS, STMicroelectronics

Make Chip: the one and only turnkey 22FDX design environment
Patrick Döll, Physical IC Design Engineer, Racyics GmbH

Keysom Studio - Design Space Exploration of processor architectures
Luca TESTA, Cofounder & COO, Keysom

Standard EDA tools based asynchronous design flow
GODARD Adrien, PhD student, STMicroelectronics

The network evolution and radio implications
Fredrik Tillman, Head of Integrated Radio Systems, Ericsson

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