D&R News Alert
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October 27th, 2022
In this issue
• Analog Bits to Demonstrate Pinless PLL and Sensor IP in TSMC N4 and N5 Processes at TSMC 2022 North America Open Innovation Platform® Ecosystem Forum
• GUC GLink™ Chip Leverages proteanTecs’ Die-to-Die Interconnect Monitoring
• Flex Logix EFLX4K eFPGA IP Core on TSMC 7nm Technology Now Available
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Welcome to the issue of October 27th, 2022 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

Foundry News
Foundry Ecosystem
Analog Bits revolutionizes SoC development in modern CMOS processes with its Pinless PLL and Sensor IP in TSMC N5 and N4 processes

Interview with Mahesh Tirupattur - Executive VP Sales, Marketing & Operations - Analog Bits Inc.  Listen Now >>

3D Packaging, Interconnect
Defacto’s SoC Compiler, the best IP Integration solution
Defacto Tech. • A fully automated Front-end SoC integration Platform
• Leverage reusability of Soft IP cores and subsystems
• Unified management of RTL, IP-XACT, UPF, SDC, LEF/DEF
• Rich & Open APIs for customization Tcl, Python, C++
Learn more >>

Design Tools
RISC-V
Dolphin Design Highlight on digital audio & processing IPs:


eFPGA
Artificial Intelligence
OL_H264ECFS H.264 Encoder with compressed frame store
Ocean Logic • Highly compressed (8-16:1) reference frame
• No DRAM required, very low power, I & P frames
• Silicon proven in automotive SoC from a major vendor
Learn more...

Internet of Things
Automotive
True Circuits • Low-jitter, pin-programmable PLL and DLL hard macros
• High-performance, general purpose and easy-to-integrate
• TSMC, UMC and GF processes from 180nm to 4nm

Learn more now >>

Business News





D&R PARTNER SPOTLIGHT

Mixel MIPI C-PHY/D-PHY Combo IP in TSMC N5
  • Silicon Proven in TSMC N5
  • MIPI C-PHY v2.0/MIPI D-PHY v2.5 compliant
  • Up to 30.78Gbps aggregate data rate
  • Supports MIPI CSI-2, DSI, and DSI-2
Learn more >>

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What they said at
IP SoC China 22

Market traction of recent video codecs: VVC & AVS3
Yujing Wei, VP of Business Development, Allegro DVT

How to satisfy growing bandwidth demands of camera, display and storage of mobile & automotive design
Kelvin Xu, Senior Product Marketing Manager, Synopsys, Inc.

AR/VR Marketing Analysis and Cadence Tensilica Solution
Wendy Chen, IP and Ecosystem Sales Group Sr Director of Asia-Pac & Japan, Cadence Design Systems, Inc.

Memory Bandwidth for AI/ML Races Higher with HBM3
Bruce Luo, Director of Sales, Rambus, Inc.

AI-ISP - Breaking Image Quality Barrier by Deeply Embedding NPU into ISP Pipeline
Kainan Cha, Vice President of Machine Learning Software, VeriSilicon Microelectronics (Shanghai) Co., Ltd.

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