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LDRA Updates Tools to Automate Worst-Case Execution Time Analysis for RISC-V
The tool suite automatically analyzes shared memory and measures worst-case execution time to ensure deterministic execution time for RISC-V processors.
allaboutcircuits.com, Mar. 29, 2025 –
Developers working on real-time and safety-critical systems—particularly in aerospace, automotive, medical, and industrial sectors—have long struggled with one persistent issue: predicting and verifying worst-case execution time in multicore environments.
With its March 2025 update, LDRA has taken a direct step to remove this barrier for RISC-V users. The company’s tool suite now automates key analysis tasks that were once time-consuming and expensive, helping engineering teams build systems that are not only safe and secure but also deterministic and certifiable.
“Fundamentally, the worst-case execution time analysis is utilized by our customers to guarantee deterministic behavior on the RISC-V architecture,” explained Jim McElroy, LDRA’s VP of sales and marketing at Embedded World 2025. “That’s really what this press release is about.”
Tackling Multicore Timing Challenges With Automation
Multicore processors boost performance by running code on multiple cores in parallel. But that comes at a cost. In many architectures, cores must share memory and cache, which introduces latency and unpredictability. One core accessing a shared cache can stall another core’s progress, and that interference can’t always be predicted or measured easily.
To manage these challenges, LDRA’s tool suite now performs automated analysis on how code interacts with shared resources—flagging access conflicts, identifying coherence risks, and measuring latency impact. These features work with RISC-V processors that include hardware-level multicore mitigation, such as Microchip’s low-latency memory allocation per core, which avoids shared cache altogether.
McElroy noted that these timing results can be captured directly from simulation environments or the physical target itself.
“We’re measuring the results of the worst-case execution times either on the host platform and simulation environment… or on the actual target hardware, which is where most of our customers do that analysis,” he said.
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