Cadence Rolls Out System Chiplet to Reorganize the SoC

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Learn more about the motivations behind Cadence’s new Arm-based system chiplet in the latest installment of The Briefing.

www.electronicdesign.com, Dec. 18, 2024 – 

The semiconductor industry is moving out of the monolithic age of the system-on-chip (SoC).

Instead of arranging every building block of IP on the same slab of silicon, the movers and shakers in the chip market are breaking them down and bundling them into separate smaller chiplets. Each of these smaller chiplets can be made using the most optimal process technology for the job in the system. Integrating all of the chips together with 2.5D packaging or 3D integration makes it possible to mimic a single large chip.

In principle, companies could take care of the chiplets at the heart of the processor–for instance, chiplets for general-purpose computing based on CPU cores, or those housing high-performance accelerators such as GPUs. Then they could choose off-the-shelf chiplets for the memory, connectivity, or other features. In practice, most companies construct the chiplets by themselves due to the cost and complexity of adopting third-party chiplets and the limited standards surrounding them.

Cadence is trying to reduce the design complexity for chiplet technology with what it called the first system chiplet. The company said it taped out the new system chiplet, which is specifically designed to serve as the central controller in the package, managing all of the resources and functionality of the multi-chiplet SoC. Developed with Arm, it communicates with the other chiplets in the package over the Universal Chiplet Interconnect Express (UCle) interface.

Cadence is one of the leading players in electronic design automation (EDA) tools used to design, simulate, and prototype chips. But it also develops many of the smaller building blocks of IP and other blueprints that are slotted into modern processors. Cadence said the system chiplet integrates Arm's processor IP with its system, memory, and interconnect IP and PHYs in a single die. It's also one of the first chiplets to comply with Arm's Chiplet System Architecture (CSA).

There are different ways to disassemble a large heterogeneous SoC into several smaller chiplets and reassemble them in a system-in-package (SiP). On that front, Arm is collaborating with Cadence and others to create a more standard approach to partitioning chiplet-based designs, enabling broader reuse of physical design and other types of IP. Arm said CSA is all about dividing complex systems into modular chiplets in the same way a monolithic chip is composed of IP blocks.

By bundling system, safety, and memory controllers and other building blocks of IP into a separate system chiplet, Cadence said it hopes to help chip designers bring new processors to market faster.

Chiplets: The Wave of the Future for Heterogeneous SoCs

The semiconductor industry is shifting to chiplets to solve some of the challenges faced by heterogenous SoCs, which are becoming prohibitively costly and complex as Moore's Law slows down.

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