What RISC-V Means for the Future of Chip Development

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csis.org, Nov. 13, 2024 – 

Many believe that the future of chip design–and the development of new technologies like next-generation artificial intelligence (AI)–will depend on RISC-V architecture. RISC-V is an open standard developed through international collaboration. Participating in international standards like RISC-V is perceived as enabling firms to maintain greater control over their intellectual property and strengthen innovation across public and private sectors. However, some U.S. policymakers also worry that the RISC-V architecture standard could endanger U.S. national security and competitive advantage.

Q1: What is (and isn't) RISC-V?

A1: An instruction set architecture (ISA) determines how software controls a processor's hardware. It instructs a chip on what to do, including how to handle data or perform memory operations. Chip designers implement ISAs in their own ways to build their own chips. Currently, designers of specialized AI chips, like Nvidia, often design custom in-house ISAs, whereas chips for general computing (also known as central processing units, or CPUs) usually adopt existing ISAs instead of creating new ones, citing lower costs, software compatibility, and proven reliability.

Currently, there are three leading semiconductor ISAs: x86 from Intel/AMD, ARM, and RISC-V ("Reduced Instruction Set Computing V"). ARM and Intel/AMD ISAs are proprietary, so other companies license their intellectual property (IP) or use processors based on their IP. By contrast, RISC-V is an open standard ISA, allowing chip design teams to implement the standard across various use cases without incurring expensive licensing fees.

Initially developed at the University of California, Berkeley, RISC-V is now managed by the nonprofit standards body RISC-V International, based in Switzerland. RISC-V International attracts a diverse community of 4,000+ members across 70 countries–many of which are U.S. firms, universities, community organizations, and individuals–who collaboratively develop rules for the RISC-V ISA.

It is important to note that RISC-V standard-setting does not require U.S. firms to share confidential information with other firms. Firms' sensitive IP is only used in their implementation of RISC-V, not shared through the RISC-V platform itself. RISC-V does not contain sensitive IP, nor does its cooperative development require firms to divulge such IP. Its primary feature is that its use is open and royalty free.

Q2: What are the advantages of RISC-V?

A2: As an open standard ISA, RISC-V is accessible and free to implement. It allows firms, large and small, to build their own implementations on top of the ISA, allowing them to maintain greater control over their technology and take advantage of software compatibility across the RISC-V ecosystem. Many firms that currently license ISAs from Intel/AMD or ARM are helping to develop RISC-V so that they can have another option for semiconductor architectures. A customizable, low-cost ISA option is attractive, particularly for smaller firms.

Some U.S. firms have already pinpointed the importance of RISC-V. They are rapidly investing in RISC-V–based software implementations. Indeed, in May 2023, industry leaders, including Google and Nvidia, launched the RISC-V Software Ecosystem (RISE) project, which intends to expedite RISC-V software in consumer electronics, datacenter, and automotive products. Even Intel is interested in advancing RISC-V, with a view to their future chip designs.

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