RISC-V for HPC at SC24

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hpcwire.com, Nov. 16, 2024 – 

RISC-V is an open Instruction Set Architecture (ISA), where the ISA can be thought of as the contract between the software and hardware worlds. Since RISC-V was first released around a decade ago, it has found its way into over 16 billion devices. The major difference between RISC-V and other ISAs, such as x86 and Aarch64, is that RISC-V is community-driven, meaning that any company or individual is free to join the effort, start contributing, and shape the standard to meet their needs.

Whilst RISC-V has grown enormously in fields such as embedded computing, it is fair to say that it has yet to gain common acceptance in HPC. But as we move further into the exascale era, increasing emphasis is placed on energy efficiency. The ability to better specialize the hardware to our workloads has significant potential.

We now see more realistic RISC-V hardware propositions for HPC, such as the 64-core SG2042 CPU and PCIe RISC-V-based accelerator cards. Moreover, several vendors have high-performance RISC-V-based hardware planned to be released within the next 12 months. Indeed, at the RISC-V North America Summit last month, Nvidia announced that they use RISC-V in all of their GPUs to undertake marshaling and control behind the scenes, so one could argue that RISC-V is already ubiquitous in HPC – just none of us tend to realize it!

RISC-V International is the standards body that oversees RISC-V, and the HPC Special Interest Group (SIG) is a part of this organization. The SIG represents HPC in the RISC-V community, and this group is organizing RISC-V events at SC.

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