Arteris Evolves Its Network-on-Chip Tiling to Accelerate AI Designs

Find the Latest SoC Solutions
for... Automotive... IoT... Security... Audio... Video

The NoC upgrade unlocks new scalability, performance, and power efficiency opportunities.

www.allaboutcircuits.com, Oct. 19, 2024 – 

This week, Arteris announced a significant evolution in its network-on-chip (NoC) IP products, which they claim dramatically enhances the scalability, power efficiency, and performance of system-on-chip (SoC) architectures for artificial intelligence (AI) and machine learning (ML) workloads.

All About Circuits interviewed Andy Nightingale, Arteris' VP of product management and marketing, and Gina Jacobs, VP of brand marketing, to learn about the new product firsthand.

Modular Scalability Through NoC Tiling

Arteris' NoC tiling technology can scale without requiring fundamental changes to the SoC architecture. NoC tiling refers to modular, repeatable blocks within the chip called "tiles." Each tile represents a self-contained functional unit that can be duplicated across the chip to meet the computational demands of AI workloads. Replicating these tiles scales performance by more than ten times.

Arteris' FlexNoC and Ncore IP products can scale because of its cohesive tile integration, which supports both non-coherent and cache-coherent interconnects. These architectures ensure data flows efficiently between processing units, such as CPUs, GPUs, and neural processing units (NPUs). The mesh topology is central to this design, allowing each tile to connect with the network interface units (NIUs) and enabling low-latency communication across the SoC. Ultimately, the mesh handles the data transport and simplifies the layout and routing, making it easier for designers to expand the system to meet increased computational demands.

For example, in AI applications such as deep learning and natural language processing (NLP) that require parallel processing, NoC tiling allows system architects to expand the number of processing elements (PEs) without introducing bottlenecks. Each tile is configured to be identical in function, minimizing the complexity that typically arises in large-scale SoC designs. This streamlined integration means that the tiles can be scaled to handle higher data volumes and larger models without significantly increasing the design time.

"Network-on-chip tiling effectively enables the partner to the designer to define a module or unit once and then repeat it multiple times within the same chip," Nightingale said. "That means we can scale up how efficiently a single designer can work and make life easier for them, even though the problems are getting bigger."

click here to read more...

 Back