IEDM: CFETs make progress at 5nm and 7angstrom

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Researchers from TSMC, IMEC, IBM and Samsung are all due to report on progress vertically-stacked complementary field effect transistors (CFETs) at this year's International Electron Devices Meeting (IEDM) coming up in December, in San Francisco.

www.eenewseurope.com, Oct. 11, 2024 – 

Engineers from foundry TSMC have a paper on the performance of a fully functional monolithic CFET inverter made on a 48nm gate pitch. A 48nm gate-pitch is roughly equivalent to a 5nm process

The CFET, a concept originally proposed by the IMEC research institute, is thought to be the transistor architecture to come after the gate-all-around multi-channel transistors.

The inverter a building block for many logic circuits is made from n-type nanosheet transistor stacked above a p-type nanosheet transistor. The TSMC includes backside contacts and interconnect for improved performance and increased design flexibility.

The devices made at TSMC exhibit voltage transfer characteristics up 1.2V and subthreshold slope of 74 to 76mV/V for both n- and p-type devices. This performative CFET is described as milestone in the progress of CFET technology even though it is unlikely to be inserted into commercial manufacturing at contemporary nodes. The area reduction achieved by two-transistor stacking is accompanied by manufacturing process complexity, however further dimensional scaling and stacking in a manner similar to 3D-NAND could give rise to advances in power, performance, area, and cost (PPAC).

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