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Reducing manual effort and achieving better coverage with AI and formal techniques

www.theregister.com/, Aug. 30, 2024 – Partner Content Given the size and complexity of modern semiconductor designs, functional verification has become a dominant phase in the development cycle.

Coverage lies at the very heart of this process, providing the best way to assess verification progress and determine where to focus further effort. Code coverage of the register transfer level (RTL) design, functional coverage as specified by the verification team, and coverage derived from assertions are combined to yield a single metric for verification thoroughness.

Coverage goals are usually quite high (95 percent or more) and hard to achieve. Verification engineers spend weeks or months trying to hit unreached coverage targets to ensure that the design is thoroughly exercised and bugs are not missed. Traditionally this has involved a lot of manual effort, consuming valuable human resources and delaying project schedules. Fortunately, in recent years several powerful techniques have been developed to automate the coverage process, achieve faster coverage closure, and end up with higher overall coverage.

A presentation by NVIDIA at the Synopsys Users Group (SNUG) Silicon Valley 2024 event described a project in which the coverage enhancement techniques of test grading, unreachability analysis, and artificial intelligence (AI) were highly successful. The NVIDIA team carefully measured the impact across three generations of related chips, providing an exceptionally quantitative case study. The designs involved were large, with more than 100 million coverage targets. Many blocks were multiply instantiated, with unique tie-offs for each instance.

Project A - the baseline design

On the baseline design, Project A, this design topology made coverage convergence very challenging. The tie-offs left each instance with large unreachable cones of logic whose coverage targets could never be hit by any test. Each instance required its own unique set of coverage exclusions, so each instance had to be signed off for coverage independently. As shown in the following example ( for one set of coverage targets, convergence using a constrained-random testbench was slow and a large manual effort was required to reach coverage signoff.

Click here to view Project A results.

Some important design bugs were not found until late in the project, a cause for concern. The verification engineers wanted to accelerate coverage to find bugs earlier and to reduce the amount of manual effort required. The first technique they tried on the derivative Project B was test grading, available in the Synopsys VCS® simulator. Test grading analyzes the simulation tests and ranks them according to achieved coverage. This enables verification engineers to set up simulation regressions in which the most productive tests run more often, with more seeds, than less productive tests. Coverage converges more efficiently, saving project resources.

Test grading was a good first step, but the team still faced the challenge of the many unreachable coverage targets in the design. They found an effective solution with Synopsys VC Formal and its Formal Coverage Analyzer (FCA) application (app), which determines the unreachable coverage targets in the RTL design. This eliminates the traditional quagmire in which the verification team spends enormous time and resources trying to hit coverage targets that can never be reached.

Formal analysis conclusively determines unreachable coverage targets and removes them from consideration for future simulations. This benefits the overall coverage calculation:

Excluding the unreachable coverage targets boosts total coverage by eliminating apparent coverage holes that are actually unreachable and by reducing the total number of coverage targets to be hit in simulation. This is a completely automated process. The FCA app generates an exclusions file with the specific unreachable coverage points for each unique instance in the design. As shown in graph at the link below, the combination of test grading and unreachability analysis on Project B achieved a major "shift left" in coverage by two key milestones.

Excluding the unreachable coverage targets boosts total coverage by eliminating apparent coverage holes that are actually unreachable and by reducing the total number of coverage targets to be hit in simulation. This is a completely automated process. The FCA app generates an exclusions file with the specific unreachable coverage points for each unique instance in the design. As shown in graph at the link below, the combination of test grading and unreachability analysis on Project B achieved a major "shift left" in coverage by two key milestones.

Click here to view Project A vs Project B coverage results.

Learnings from Project B

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