EDA Companies Unite With Samsung for AI and 3D IC Technology

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At DAC 2024, leading EDA companies partnered with Samsung to help realize its AI technology roadmap led by process nodes SF2Z and SF4U.

www.allaboutcircuits.com, Jun. 30, 2024 – 

It was a busy week for Samsung at the Design Automation Conference (DAC) 2024, where the manufacturer garnered support from leading EDA providers for its two SF2Z and SF4U process nodes. This news follows the same EDA companies, Cadence, Siemens, and Synopsys, announcing support for Intel's Foundry's new process technology, including the Intel 18A node.

Samsung says its new process technology, combined with its newly forged partnerships with Cadence, Siemens, and Synopsys, will enable it and foundry customers to create low-power, high-performance chips for AI workloads.

Samsung's New GAA SF2 and SF4 Nodes

The top EDA companies have optimized their tools for Samsung's gate-all-around (GAA) SF2 and SF4 node technology. GAA is Samsung's most advanced node technology, allowing node sizes as minuscule as 2 nm with up to 45% power efficiency improvement and significant gains in performance and surface area. In advanced semiconductor manufacturing, an ongoing challenge has been reducing gate length while retaining efficiency. To address this, Samsung developed the third-generation GAA structure.

In a transistor with a traditional planar structure, significant current leakage, known as a short channel, occurs between the source and drain. In GAA transistors, the gate surrounds all four sides of the channel where electric current flows. This enables better control of current flow and enhances channel operation, resulting in higher energy efficiency.

Cadence Bolsters 3D IC and AI Simulation

Cadence recently announced a broad collaboration with Samsung aimed at accelerating 3D IC and AI semiconductor development. The company says it has optimized its EDA tools for analog and digital advanced node AI designs, particularly Samsung's GAA SF2 and SF4 node technology.

Cadence says its vast Cadence.AI verification and IP suite accelerate time to market and maximize PPA for advanced process nodes. It also reportedly reduces leakage current by an average of 10%

Cadence.AI encompasses several different EDA tools: Cadence Cerebrus, Virtuoso Studio, Verisium, Allegro x AI, and Optimality. Cerebrus is an AI-driven digital design tool that automatically optimizes the design for maximized PPA based on desired constraints the designer inputs. Other tools in the Cadence.AI suite, such as Allegro x AI, use generative AI to reduce placement and routing (P&R) time from days to minutes. Additional features of Allegro x AI include auto-synthesis of power and ground planes and critical net auto-routing.

In addition to Cadence.AI, Cadence also has a full backside implementation certified for SF2 and the Cadence Integrity 3D-IC Platform for multi-die integration.

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