Imec Demonstrates Capacitor-less IGZO-Based DRAM Cell With >400s Retention Time

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Back-end-of-line compatible architecture paves the way to high-density 3D-DRAM memories Back-end-of-line compatible architecture paves the way to high-density 3D-DRAM memories

LEUVEN (Belgium) -- December 3, 2020 — At the 2020 International Electron Devices Meeting, imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, presents a novel dynamic random-access memory (DRAM) cell architecture that implements two indium-gallium-zinc-oxide thin-film transistors (IGZO-TFTs) and no storage capacitor. DRAM cells in this 2T0C (2 transistor 0 capacitor) configuration show a retention time longer than 400s for different cell dimensions – significantly reducing the memory’s refresh rate and power consumption. The ability to process IGZO-TFTs in the back-end-of-line (BEOL) reduces the cell’s footprint and opens the possibility of stacking individual cells. These breakthrough results pave the way towards low-power and high-density monolithic 3D-DRAM memories.

Scaling traditional 1T1C (one transistor one capacitor) DRAM memories beyond 32Gb die density faces two major challenges. First, difficulties in Si-based array transistor scaling make it challenging to maintain the required off-current and world line resistance with decreasing cell size. Second, 3D integration and scalability – the ultimate path towards high-density DRAM – is limited by the need for a storage capacitor. Imec presents a novel DRAM architecture that responds to both challenges, thereby offering a scaling path towards low-power high-density 3D-DRAM memories.

The new architecture implements two IGZO-TFTs – which are well known for their very low off-current – and no storage capacitor. In this 2T0C configuration, the parasitic capacitance of the read transistor serves as the storage element. Resulting DRAM cells exhibit a retention time >400s thanks to an extremely low (extracted) off-current of 3x10-19A/µm. These breakthrough results were obtained for optimized scaled IGZO transistors (with 45nm gate length) processed on 300mm wafers. Optimization was directed towards suppressing the impact of oxygen and hydrogen defects on both on-current and threshold voltage – one of the main challenges for developing IGZO-TFTs.

Gouri Sankar Kar, Program Director at imec: “Besides the long retention time, IGZO-TFT-based DRAM cells present a second major advantage over current DRAM technologies. Unlike Si, IGZO-TFT transistors can be fabricated at relatively low temperatures and are thus compatible with BEOL processing. This allows us to move the periphery of the DRAM memory cell under the memory array, which significantly reduces the footprint of the memory die. In addition, the BEOL processing opens routes towards stacking individual DRAM cells, hence enabling 3D-DRAM architectures. Our breakthrough solution will help tearing down the so-called memory wall, allowing DRAM memories to continue playing a crucial role in demanding applications such as cloud computing and artificial intelligence.”

(a) Schematic of a 2T0C DRAM cell, where the storage element is the oxide capacitance Cox of the read transistor; (b) example of a schematic top-view of a 2T0C DRAM array on a single planar level. The A-A’ cross-sectional direction indicates that the array density can be increased by (c) stacking several layers of the 2T0C cell.

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