300Mn gate Data Centre SoC challenges and PPA insights.

Maulik Patel - eInfochips- Physical Design Lead

Biography :

Maulik has experience in ASIC implementation for Mobile CPU, Wireless, DDR-IP, Network SoC. He has done multiple tape out for Qualcomm, Broadcom, Cypress, Cadence and Juniper networks . Maulik is currently working with eInfochips-Arrow on 16nm ASIC design as Technical Lead-II. His main interests are Low Power Implementation, Clock Tree Synthesis for High frequency design, IP Hardening.