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NEWS

Why join IP SoC Santa Clara 2019?

IP-SoC Santa Clara 2019 is the unique one day working conference fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems.

The event is the annual meeting in the Valley for IP providers and IP consumers to share information about Technology trends, Innovative IP/SoC products, Breaking IP/SoC News, IP/SoC Market evolution and more.

Meet the gurus in the field and Get the best vision to orientate your business.

Where : HYATT REGENCY SANTA CLARA
5101 Great America Pkwy, Santa Clara, CA 95054, USA

Click here to register >>

Program
 Welcome
8:40 am IP Provider the vital seed of Electronic industry

By Gabriele Saucier
CEO & Founder
D&R
 More Intelligence and Security needed
Chair : Gabriele Saucier, D&R.
8:55 am Overcoming AI SoC Design Challenges with IP

By Ron Lowman
Strategic Marketing Manager
Synopsys, Inc.
9:15 am Machine learning on ultra-constrained devices

By Mark Woods
Principal Solutions Architect
Arm
9:35 am Protecting a Connected World with Embedded Security IP

By Ben Levine
Sr. Director of Product Marketing for Cryptography
Rambus, Inc
 Data Storage and Big Data
Chair : Olivier Bernard, Arm
9:55 am High-Performance Interface IP:  When Big Data Meets Big Compute

By Sundar Gopalan
Product Marketing Director
Cadence Design Systems, Inc.
10:15 am Memory-centric hardware acceleration for machine intelligence

By Sylvain Dubois
Vice President of Strategic Marketing & Business Development
Crossbar, Inc.
10:35 am Platforms for SSD and IoT Applications

By Amit Saxena
VP of Engineering
Mobiveil, Inc.
10:55 am Break
 New era in IP Management, Business contracts and Collaboration
Chair : Rita Horner Synopsys, Inc.
11:15 am Chip Design ≠ Taxi Business: Rethinking Collaborations

By Samir Patel
CEO
Sankalp Semiconductor
11:35 am IP Management using Blockchain Technology and Smart Contracts

By Mukund Pai
SoC Power Lead
Intel Corporation
11:55 am From smart Delivery to smart Contracts. Is Core Store a Myth?

By Gabriele Saucier
CEO & Founder
D&R

And Pascal Adam
Product Marketing Manager at SST - A Microchip Technology Company
Microchip Technology Inc.
 Panel and Lunch
12:15 pm IP Democratization: Which enablers? New Business model, IP central or Design Market Place...

IP democratization is not a choice but a necessity for IP business survival
This panel aims at addressing both facets of the same coin :
  • New business models & contracting process
  • IP dissemination or collaborative design platform
With the participation of Olivier Bernard (Arm), Frankwell Lin (Andes Technology Corporation & RISC-V Foundation), Samir Patel (Sankalp Semiconductor), Sunil Shenoy (SiFive), Mukund Pai (Intel Corporation), Mike Wishart (efabless corporation).
Lunch
 SoC Design and Security
Chair : Samir Patel, Sankalp Semiconductor
2:00 pm Next Generation of SoC Design flow ­‐ From Atoms to System solutions

By Babak Taheri
CTO and EVP of Products
Silvaco, Inc.
2:20 pm Hardware monitoring and analytics provide the tools for optimization at scale

By John Hartley
VP Global Sales
UltraSoC
2:40 pm Securing Your SoC

By Peter Dumin
Sr Application Engineer
CAST, Inc.
3:00 pm Flexible and scalable IP to secure a wide variety of devices and markets

By Pieter Willems
Director Sales and Marketing
Silex Inside
3:20 pm Break
 From Analog to DSP
Chair : Wendy Wu, Cadence Design Systems, Inc.
3:50 pm Is efficient Analog IP reuse a myth? An innovative Approach to make Analog IP reuse a reality

By Sowmyan Rajagopalan
Founder & CTO
Thalia Design Automation
4:10 pm ADCs for Autonomous Driving

4:30 pm A New DSP Approach for 5G and AI

By Albert Camilleri
VP Business Development North America
VSORA
4:50 pm Designing IP Cores for Advance Digital Signal Processing

By Sudhir Singh & Chatu Lokuge
Distinguished Wireless Research Engineer & Team Leader, RTS Communication
IP Coreworx & Callaghan Innovation
 Power Management and Memory
Chair : Mukund Pai, Intel Corporation
2:00 pm Power Management for IoT SOC Development

By Stephen Nolan
Vice President of Sales and Business Development
Vidatronic, Inc.
2:20 pm Top 10 Techniques to Reduce Power & Cost with optimum selection of Memory IPs for SOCs

By Farzad Zarrinfar
Managing Director, IP Division
Mentor, a Siemens Business
2:40 pm Break
 Innovative IP for New Applications
Chair : Vaibhav Tripathi, Omni Design Technologies, Inc.
3:10 pm Fast yet Low Power RISC-V Core IP for SoC Designers

By Frankwell Lin
President
Andes Technology Corporation
3:30 pm The USB roadmap for Video and AR/VR applications

By Ali Khan
VP of Business and Product Development
Corigine Inc.
3:50 pm Comparing silicon to simulations for a 1.3pJ/bit 25Gbps SerDes Rx in 28nm

By Andrew Cole
VP Business Development
Silicon Creations
4:10 pm Enabling 400G Networking with 56G Ethernet PHY IP

By Rita Horner
Sr. Technical Marketing Manager
Synopsys, Inc.
4:30 pm Unleashing the Power of AI and ML in the Cloud through a pay-per-use business model

By Jin Zhang
VP Marketing
Algodone

INDUSTRY SPONSORS
Arm
Synopsys
Cadence
Rambus
Mentor
Cast
Corigine
Sankalp
Silicon Creations
Sifive
Siliconch
Sofics
Amphion
VSORA
Vidatronic
Mobiveil
Silvaco
Andes
Credo Semiconductor
Ultrasoc
IP Core Worx
Thalia Design Automation
Algodone
Numem


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