Company
design-reuse.com
D&R China
D&R Events
Videos
Sign In

www.design-reuse-embedded.com
SEARCH IP   
    • Categories
    • RISC-V
    • Embedded Processing
    • 5G, 3GPP LTE IP
    • IoT IP
    • Artificial Intelligence IP
    • Automotive IP
    • Space and Avionics
    • Security IP
    • Audio & Video IP
    • Design Platforms
    • Monitoring and Verification
    • SoC Design Services
    • Find your best SoC design partner
Partner Videos D&R Events
    • IP-SoC Days 2025
    • IP-SoC Days 2024
    • IP-SoC Days 2023
    • IP-SoC Days 2022
    • IP-SoC Days 2021
    • IP-SoC 2024
    • IP-SoC 2023
    • IP-SoC 2022
    • IP-SoC 2021
NEWS

Scaling AI Infrastructures for the Future with Next-Gen Interconnects
Aparna Tarde - Sr. Staff Technical Product Manager - Synopsys, Inc.
Biography :
Aparna Tarde is a Sr. Staff Technical Product Manager responsible for the die-to-die interface IP product line at Synopsys. She previously worked as a design engineer at Intel designing cloud-based accelerator systems using PCIe, Ethernet, and DDR. She has also held different positions from design verification to applications engineering and has extensive knowledge in system design using FPGAs in data centers. She holds a master's degree in electrical engineering from San Jose State University.

Partner with us

Contact Us
Partnership Offers

List your Products

Suppliers, list and add your products for free.

List your Products

More about D&R Privacy Policy

© 2024 Design And Reuse

All Rights Reserved.

No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse.

I understand
This website uses cookies to store information on your computer/device. By continuing to use our site, you consent to our cookies. Please see our Privacy Policy to learn more about how we use cookies and how to change your settings if you do not want cookies on your computer/device.