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8:30 am
Welcome
Chairperson: Yu Byoung Du, KSIA
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Opening talk from KSIA Vice Chairman
Jeong-Hoi Kim
ViceChair
KSIA
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Welcome to IP-SoC Community
Gabrièle Saucier
CEO
Design And Reuse
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9:00 am
Analog IP
Chairperson: Yu Byoung Du, KSIA
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Analog IP Solution for SAMSUNG Foundry
Myeon-Lyong Ko
R&D Center Director
LeoLSI
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Power Management Sensor IP’s for FinFet and GAA processes
Mahesh Tirupattur
Executive Vice President
Analog Bits Inc.
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Break
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10:00 am
Interface and Connectivity IP
Chairperson: Yu Byoung Du, KSIA
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LPDDR Support on Mature Technology Nodes
Dave DongHun Kim
Senior Manager, FAE
OPENEDGES Technology, Inc.
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Beyond the interface IP
Tae-Pyeong Kim
Cadence Design Systems, Inc.
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UCIe Progress Report: Big Enhancements, IP Maturity, and Ecosystem Interoperability
Hyoung-Bae Choi
Sr. Director
Synopsys, Inc.
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Break
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11:20 am
RISC-V
Chairperson: Yu Byoung Du, KSIA
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Leveraging the RISC-V Efficient Trace (E-Trace) Standard
Processor trace gives developers access to critical insights and forensic capabilities to manage the risk of building embedded systems. Siemens, a lead technical contributor to the RISC-V Efficient trace (E-Trace) specification, will cover an overvie w of the trace specification and discuss how processor trace is used to improve embedded software and applications.  ... 
Soo Yong Lee
Account Technology Manager
Siemens
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Imagination APXM-6200 CPU: Performance meets Trust in RISC-V
JongChan (Brian) Mun
Senior Sales Director
Imagination Technologies Group Ltd.
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Lunch Break
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1:00 pm
Artificial Intelligence
Chairperson: Mahesh Tirupattur, Analog Bits
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Scalable, Flexible Edge AI accelerator: Silicon-Proven IP for Consumer Electronics
Kwak Jaehwa
CTO
AiM Future, Inc.
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Meeting the Needs of AI Training with HBM3E
AI training models are growing in both size and sophistication at a lightning pace, requiring greater and greater bandwidth. With its unique 2.5D/3D architecture, HBM3E can deliver Terabytes per second of bandwidth. Join Rambus to hear how HBM3E meet s the memory needs of state-of-the-art AI training models. ...
Suk Keun Youn
Director of Sales
Rambus, Inc.
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AI on RISC-V
Hojung Han
Staff Applications Engineer
Imagination Technologies Group Ltd.
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Break
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2:20 pm
Video
Chairperson: Philippe Flatresse, Soitec
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Future of ISP ( Camera ISP & Display ISP )
Brief introduction of ISP history and future ISP* *Image Signal Processor
Daeha Kook
Director
BTREE Co. Ltd.
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AI-based video pre-processor to reduce the storage cost and network traffic for video applications
Hyung-Seok Han
Director of Marketing
BLUEDOT
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Break
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3:20 pm
Security and High Safety Solutions
Chairperson: Philippe Flatresse, Soitec
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Quantum Safe Cryptography: Protecting Devices and Data in the Quantum Era
Quantum computers will eventually become powerful enough to break current asymmetric encryption, placing important data and assets at risk. In this presentation, Rambus will discuss recent developments in Quantum Safe Cryptography and highlight what you need to know to protect devices and data in the quantum computing era. ...
Jihan Moon
Senior Principal Engineer in Field Application Engineering
Rambus, Inc.
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PUF based Root of Trust for Emerging Post Quantum Cryptography
Duhyun Jeon
Senior Engineer
ICTK
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AI-powered cybersecurity: Securyzr™ Intrusion Detection System (IDS)
Ahmed BOUGRIANE
Pre-Sales Engineer North Asia
Secure-IC
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How SafeIP(TM) enables fail operational vehicles, robotics and drones
Diana Strohbach
Head of Marketing & Collaboration
Siliconally GmbH
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4:40 pm
Monitoring & Design Platform
Chairperson: Philippe Flatresse, Soitec
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The Critical Role of Embedded Monitor IP in Enabling Silicon Lifecycle Management Use Cases
To keep pace with the ever-growing performance demands of cutting-edge applications like HPC and Automotive, device and system complexity continues to increase. The emergence of multi-die technology has also compounded this complexity. To meet these demands, designers can optimize both the health and performance of their silicon by gathering meaningful data at each stage of the device lifecycle from silicon to system that can provide actionable insights for intelligent decision making. Silicon Lifecycle Management (SLM) is built on a foundation of in-chip monitors IP, data analytics and design automation. Environmental, structural and functional monitors enable these actionable insights which can be leveraged from the early In-Design phase through In-Ramp, In-Production and ultimately In-Field operation. In this presentation we will explore how SLM IP monitors, EDA tools and methodologies are the driving force behind intelligent data collection, storage and analysis which enables popular SLM use cases such as Vmin Optimization, Adaptive Voltage Scaling (AVS), Silicon Model Correlation, Process Classification, Mission Profile Analytics, Predictive Maintenance and Remaining Useful Life (RUL). ...
Sangmin Lee
Project/Program Manager EDA Group
Synopsys, Inc.
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The Advantages of Using HW Stacks in Your Design
Dr. Calliope-Louisa Sotiropoulou
Sales Engineer
CAST, Inc.
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