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Security Verification in SoCs
Ali Hmedat - Senior Design vérification Engineer - AEDVICES CONSULTING
Biography :
| Principal design and verification Engineer with over 12 years of experience in the semiconductor industry. My passion lies in chip design and verification, and I have developed a strong skill set in this field. As a chip design verification engineer, I possess a high level of expertise in functional verification methodologies. I am proficient in using System Verilog based UVM (Universal Verification Methodology), Specman e, ERM (e Reuse Methodology) architecture, assertion-based verification, formal equivalent modeling, and building scoreboards. These tools and techniques allow me to ensure the highest quality and reliability of chip designs, meeting the most stringent industry standards. One of my core strengths is the ability to effectively utilize Synopsis tools like VCS, VERDI, and Z01X, streamlining the verification process and accelerating project outcomes. As a leader, I excel in team building and management. I have a proven track record of fostering collaborative and motivated teams. My leadership approach revolves around empowering team members, encouraging their professional growth, and promoting open communication. By delegating tasks strategically and providing guidance, I ensure that our team operates cohesively, producing exceptional results in the projects we undertake. Throughout my career, I have demonstrated adaptability and resilience in leading teams through change and tackling challenging projects. My ability to navigate through various design and verification processes seamlessly contributes to the success of our projects. In addition to my technical expertise, I am skilled in diagnosis analysis for functional safety requirements based on the ISO 26262 standard. This dedication to adhering to safety guidelines ensures that our designs meet the highest industry standards and deliver top-notch functional safety. |
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