A worldwide connected Event !!
IP-SoC 2024 is the 27th edition of the working conference fully dedicated to IP (Silicon Intellectual Property) and IP based electronic systems.
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9.00 am
Welcome Session
Chairperson: Philippe Quinio - STMicroelectronics
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IP SoC Community: EU as a main player ?
Gabrièle Saucier
CEO
Design And Reuse
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The network evolution and radio implications
Fredrik Tillman
Head of Integrated Radio Systems
Ericsson
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Increased competitiveness and sustainability in connectivity with advanced substrates solutions
Francois Brunier
Partnership Program Manager
Soitec
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Chips Act and EU design Platform
Olivier Thomas
CEA
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Break
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11.00 am
Interface IP
Chairperson: Olivier Thomas - CEA
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The Critical Role of PCIe 7.0 & CXL 3.1 Solutions in Enabling AI applications
Bart Stevens
Senior Director of Product Marketing
Rambus, Inc.
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IoT Solutions
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How to select the best Audio codec architecture to enhance your wearables?
Discover the latest advancements in IP for headset amplification, including Class A/B, Class D, and open or closed-loop systems. Learn how these IP innovations optimize sound quality, efficiency, and power consumption, offering a competitive edge in product development for high-performance audio devices.  ... 
Etienne Faucher
Product Marketing Manager
Dolphin Semiconductor
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Wireless and Batteryless Interface for IoT
Polina Proskurova
Project Manager
NTLab
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Lunch Break
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1.00 pm
Automotive Solutions
Chairperson: Chris Brown - SST
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Driving Sustainability in Automotive Electronics; Innovating for a Greener Future
Philippe Flatresse
Product Marketing
Soitec
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Silicon Lifecycle Management (SLM) in context of Chiplets for Automotive
Graham Woods
Principal Product Manager
Synopsys, Inc.
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Protecting Automotive Networks with MACsec Security
Bart Stevens
Senior Director of Product Marketing
Rambus, Inc.
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Cyber Resilience and Safety in Automotive: How Security IP Provides Essential Primitives for Compliance
Gordon Fairley
Kudelski IoT
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Break
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2.45 pm
Security IP
Chairperson: Bart Stevens - Rambus, Inc.
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Secure-IC Differential Loop PUF : Overcoming some weaknesses of the traditional Loop PUF while enhancing its usability
In this presentation we expose the concept of the Differential Loop PUF, as well as some significant data showing its advantages in terms of security as well as of flexibility of usage
Brice GAIGNOUX
Pre-Sales Engineer EMEA
Secure-IC
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The CHERI Alliance - getting security embedded into electronic systems
The worldwide cost of cyberattacks now reaches an estimated $10 trillion per year. Memory safety issues continue to be the main source of cyber security problems and have consistently represented ~70% of vulnerabilities over the past 20 years. There fore, there is a strong and increasing interest in CHERI (Capability Hardware Enhanced RISC Instructions), a technology that mitigates memory safety vulnerabilities by design. It provides security features at the hardware level that can be leveraged by the software to provide more robust security. It has been developed by University of Cambridge and other research labs, and after 14 years of improvement and tuning, it is now ready to go into products. However, getting the industry to adopt a new security technology requiring new hardware, from processor IP to end products. This is not something that will happen without a proactive and coordinated effort. This is the goal of the CHERI Alliance, a non-profit organisation created to accelerate the adoption of the technology. This talk provides an overview of the CHERI technology: the benefits it provides, an overview of how it works, and the constraints associated with its integration. It also introduces the CHERI Alliance: its objectives, its means and its roadmap. ...
Mike Eftimakis
Founding Director
CHERI Alliance
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Integrated Security Solutions: How SRAM-based PUF Augments Embedded Hardware Secure Modules in a Post-Quantum World
Erik van der Sluis
Principal R&D Engineer
Synopsys, Inc.
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Security Verification in SoCs
As System-on-Chip (SoC) designs become increasingly complex and interconnected, ensuring their security has become a critical challenge for the semiconductor industry. Modern SoCs are embedded in everything from mobile devices and autonomous vehicles to industrial equipment and IoT devices, making them prime targets for security attacks. Security breaches can result in catastrophic consequences, including loss of data, privacy violations, and compromised critical infrastructure. This presentation will explore the emerging importance of Security Verification in the SoC design lifecycle, highlighting the growing need to verify hardware against sophisticated attacks and vulnerabilities. While traditional verification methods focus on functionality and performance, security verification requires additional layers of checks to protect against malicious tampering, side-channel attacks, and unauthorized access. ...
Ali Hmedat
Senior Design vérification Engineer
AEDVICES CONSULTING
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Break
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4.20 pm
Wireless Solutions
Chairperson: Mike Eftimakis - CHERI Alliance
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InCirT Pioneers High-Performance Data Converter Technologies for Next-Gen Wireless Communications
InCirT GmbH, based in Aachen, Germany, develops high-performance data converter technologies crucial for next-gen applications like 5G, radar, and satellite communications. Our innovations, such as the FDDAC and FDADC architectures, enable ultra-wide modulation bandwidth, high signal quality, and energy efficiency. These solutions support software-defined radios and high-speed wireless links, including markets for Wi-Fi 8 and mmWave Wi-Fi. Besides our flagship data converters we provide various Semiconductor IP for PLLs, LDOs, ADCs, and DACs. ...
Dr.-Ing. Oner Hanay
CEO
InCirT GmbH
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Battle of the Bits: Evaluating Lossless Data Compression Algorithms and Cores
This presentation provides a comprehensive comparative analysis of lossless data compression cores and algorithms, focusing on their efficiency, performance, and practical applications. The study examines key algorithms such as GZIP, LZ4 and ZStd, ev aluating them in terms of compression ratios, speed, hardware resource usage, and scalability. The goal is to equip engineers, system architects, and decision-makers with actionable insights to select the most suitable compression approach for their specific needs. ...
Dr. Calliope-Louisa Sotiropoulou
Sales Engineer
CAST, Inc.
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Break
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5.30 pm
Open Panel: Greener Electronics: a myth or a reality ?
Chairperson: Patrick Blouet
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6R Greenness Profiling for IC and Boards
Gabrièle Saucier
CEO
Design And Reuse
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IC Life time modeling : a critical parameter for Greener Electronics
HN Nguyen
CTO
METASymbiose
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Strategic decision-making in the semiconductor sector: shifting from relative to absolute sustainability
Thibault Pirson
PhD, research assistant
UCLouvain
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9.00 am
Analog & Digital Design
Chairperson: Florian Bilstein - Racyics GmbH
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How to Enhance Energy Efficiency and Reduce Costs with Advanced In-Situ Sensors?
Dolphin’s patented in-situ slack-time monitors, the Slack Guards, enhance the energy efficiency of standard Adaptive Voltage Scaling (AVS) solutions while reducing the related costs. For ultimate gain at even lower costs, Slack Guards enable the on-chip integration of fully-digital, real-time AVS platforms, regardless of the process considered. ...
Vincent Telandro
Product Marketing Manager
Dolphin Semiconductor
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Standardizing CDC and RDC abstract models
CDC analysis has evolved as an inevitable stage in RTL quality signoff in the last two decades. Over this period, the designs have grown exponentially to SOC’s having 2 trillion+ transistors and chiplet’s having 7+ SOC’s. Today CDC ver ification has become a multifaceted effort across the chips designed for clients, servers, mobile, automotives, memory, AI/ML, FPGA etc. with focus on cleaning up of thousands of clocks and constraints, integrating the SVA’s for constraints in validation environment to check for correctness, looking for power domain and DFT logic induced crossings, finally signing off with netlist CDC to unearth any glitches and missing crossings during synthesis. As the design sizes increased in every generation the EDA tools could not handle running flat and the only way of handling design complexity was through hierarchical CDC analysis consuming abstracts. Also, hierarchical analysis helps to enable the analysis in parallel with teams across the globe. Even with all these significant progress in capabilities of EDA tools the major bottleneck in CDC analysis of complex SOC’s and Chiplets is consuming abstracts generated by different vendor tools. Different vendor tool abstracts are seen because of multiple IP vendors , even in house teams might deliver abstracts generated with different vendors tools. The Accellera CDC Working- Group aims to define a standard CDC IPXact model to be portable and reusable regardless of the involved verification tool.As moving from monolithic designs to IP/SOC with IPs sourced from a small/select providers to sourcing IPs globally (to create differentiated products), the quality must be maintained as driving faster time-to-market. In areas where the standards (SystemVerilog, OVM/UVM, LP/UPF) are present, the integration is able to meet the above (quality, speed). However, in areas where standards (in this case, CDC) are not available, most options trade-off either quality, or time-to-market, or both :-(Creating a standard for inter-operable collateral addresses this gap.This tutorial aims to remind the definitions of CDC-RDC Basic Concepts and constraints, as well as the description of the reference verification flow, and addressing the goals and scope of the Accellera CDC Working Group in order to elaborate a specification of the standard abstract model. ...
Jean-Christophe Brignone
SMTS
STMicroelectronics
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Break
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10.00 am
Design Platform and Design Flow
Chairperson: Erkan Isa - Fraunhofer-Gesellschaft
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Make Chip: the one and only turnkey 22FDX design environment
Patrick Döll
Physical IC Design Engineer
Racyics GmbH
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Keysom Studio - Design Space Exploration of processor architectures
Keysom introduces Keysom Studio, the first no-code tool for design space exploration of processor architectures. Users can compare as many configurations as wanted and instantly get reports on metric as Kilo Gate Equivalent, silicon area, power consu mption. Users can then test them on FPGA before integration of the chosen IP. ...
Luca TESTA
Cofounder & COO
Keysom
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Standard EDA tools based asynchronous design flow
This work introduces a synthesis flow reusing traditional EDA tools for bundled data circuits design. By combining a graph-based circuit representation with the existing local clock set (LCS) methodology, which translates asynchronous timing requirem ents into standard tool constraints, a generic approach supporting a wide variety of asynchronous protocols is achieved. ...
GODARD Adrien
PhD student
STMicroelectronics
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Automated Abstractions: High-Level Model Generation from Design Specifications or RTL Descriptions
ANDRIAMISAINA Choukataly-Caaliph
CEA
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Break
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11.40 am
Migration and Yield Consideration
Chairperson: HN Nguyen - METASymbiose
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Porting ASIC IP Cores to FPGA: It's Not a Cakewalk!
Manufacturers of semiconductor IP cores support complex ASIC projects, some of which include extreme requirements in terms of clock speeds, area utilization, power consumption, reliability, functional safety, and reusability—and all of which com e with high expectations for predefined circuit parts. Anyone who decides not to develop a certain functionality themselves, but rather to obtain it through a partner, accepts the purchased component’s functionality as a foregone conclusion. It is assumed that the use of IP cores from reputable suppliers will go smoothly. Since the areas of end-application for one and the same IP core can be completely different, the IP core provider must take all possible areas of application into account, in order to avoid disappointing their customers. If a function—for example, a MIPI CSI-2 Receiver/Transmitter IP or USB interface—is used in a consumer product that is sold millions of times, the requirement is different than when the IP core is used in the "hot area" of a fighter plane manufactured in limited quantities. For one user, the definition of success might be a reduction of silicon area. For another, it could mean lowest power consumption or maximum reliability, even under harsh operating conditions. In most cases there is another important point to consider. The IP core should not only “land” on the ASIC, but also be used as part of FPGA-based prototyping. It is well understood that ASICs require a great deal of care in their development, yet sadly often underestimated that an FPGA requires very special attention as well, and in its own unique way. To put it bluntly: porting ASIC IP cores to FPGA is not a cakewalk—but if the process is approached methodically, success is attainable! This talk outlines, at a high level, everything that must be considered when porting ASIC IP cores to FPGA, centering on a practical example using SmartDV’s USB3.2 Gen2x1 Device IP. ...
Philipp Jacobsohn
Principal Application Engineer
SmartDV Technologies
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Niche gets super niche in the SEMI conductor Equipment domain
Synopsys: Imagine a process that is 99% of the time is accurate and meet its specifications in terms of output. Now, the same process is divided in to 100 steps and each step running at 99% accurate, yet the overall process efficacy in the second ca se becomes a depressing 64% ? (99/100*99/100 …100 times). As you can witness, when the process becomes more and more granular, it is way more difficult to sustain the current level of accuracy let alone improve it. That is what we are witnessing in semiconductor domain. As the process gets progressively nuanced, despite developing tools which are way more sophisticated, it is getting really challenging to sustain the yield. The presentation will delve in to specific aspects of SEMI manufacturing equipment side as a case study. What are the tools that were deployed? Ongoing lessons that are learnt. Impact of Automation using Gen-AI //End of abstract //12th October 2024, Bangalore, INDIA ...
P SRINIVASA RAGHAVAN
Practice Head, Semiconductor BU
HCL TECH
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Lunch Break
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1.15 pm
What's new on FDSOI: the SOIL Project
Chairperson: Philippe Flatresse - Soitec
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Solidify the European FDSOI ecosystem and accelerating its industrial deployment; A Chips JU initiative
Martin LABRUNE
European & France Public Affairs
STMicroelectronics
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Designing Intelligence from our SOIL
Krishna Pradeep
Soitec
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Innovating the Future with SOIL: Next-Gen IPs, Transfer from Research to Silicon
Damian Panter
Fraunhofer
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From silicon to the use cases, SOIL as a test bench for automotive applications
Leonardo Govoni
AED Vantage GmbH
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Break
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3.00 pm
FDSOI IP
Chairperson: François Brunier - Soitec
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Market Available FDSOI IP
Dagmara Zielinska
Partnership Program Manager
Design And Reuse
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Designing SOC with ABX® - Challenges and Solutions
22FDX® technology enables post silicon adaption of transistor threshold voltages by Adaptive Body Biasing (ABB) which is extensively used by the Racyics® ABX® Platform. ABX dynamically compensates PVT variations, thereby providing reliable ultra-low voltage (ULV) operation down to 0.4V. This presentation shows ABB partitioning concepts using an ULV SoC example. ...
Florian Bilstein
Director Design Service
Racyics GmbH
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Ultra-wide band digital-to-analogue converter for wireless communication
Dr.-Ing. Oner Hanay
CEO
InCirT GmbH
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4.00 pm
Break
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4.20 pm
Panel: Building a strong FDSOI Ecosystem: A Catalyst for Tomorrow's market wide Applications
Organizer:
Philippe Flatresse - Soitec
FDSOI Technology has been over for quite a long time. This panel will investigate whether or not the technology and Ecosystem supporting this technology worldwide have now reached its full maturity or are still in a growing phase. The panel groups FDSOI technology specialists, FDSOI Business managers, researchers and FDSOI IP providers.
With the participation of:
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Olivier Thomas CEA
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Rainer Lutz Soitec
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Anton Klotz Fraunhofer
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Florian Bilstein Racyics GmbH
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Michel Vasmer Capgemini Engineering
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