When : September 12th, 2024
Where: Evergreen Laurel Hotel Shanghai
No. 1136, Zu Chongzhi Road, Pudong New District
Pudong, 202203 Shanghai, China
Join D&R IP SoC China 24 !! A worldwide connected Event !!
Co-organized with:
A worldwide connected Event !!
D&R IP-SoC China 2024 Day is the unique worldwide event in China fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems.
IP-SoC providers, the seed of innovation in Electronic Industry, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry.
IP consumers can view at a glance the latest Technology trends and exciting Innovative IP/SoC products. Through a global view, Electronic systems leaders may identify disruptive innovation leading to new market segment growth.
The event is a face to face meeting. In order to enhance the market attention the talk material and videos are posted concurrently on www.design-reuse-china.com and Youku.
Any question? Please contact us
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8:45 am
Welcome Session
Chairperson: Gabrièle Saucier, D&R
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Welcome to the IP SoC community
Gabrièle Saucier
CEO
Design And Reuse
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The new trend of IP in the integrated circuit industry
Dr. Junyu Chen
Assistant to the Chairman of GTA Semiconductor
GTA Semiconductor
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Adding Intelligence in Green Technology
Alex LIM JAN PANG
Business Development
SOITEC
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Break
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10:00 am
Design Platform
Chairperson: Philippe Flatresse, Soitec
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From design to mass production, a one-stop IP and customization service platform for LLM system
Louis Li
Vice President of FAE
Innosilicon
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A One-stop IP Solution and Turnkey SoC Platform for Intelligent Life
Marshall Li
Project Director
Brite Semiconductor Shanghai Co. Ltd.
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Designing Next-Gen SoCs using Cadence Tensilica IPs to enable Pervasive Intelligence at the Edge
Wei Wang
AE Director
Cadence Design Systems, Inc.
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The Advantages of Using HW Stacks in Your Design
Dr. Calliope-Louisa Sotiropoulou
Sales Engineer
CAST, Inc.
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11:20 am
Verification Platform
Chairperson: Philippe Flatresse, Soitec
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Kalray optimizes complex software with Tessent Enhanced Trace Encoder
Yifan Li
Tessent Account Technology Manager
Siemens
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The Critical Role of Embedded Monitor IP in Enabling Silicon Lifecycle Management Use Cases
Alex Yu
Solutions Engineering, Sr Manager
Synopsys, Inc.
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1:00 pm
RISC-V
Chairperson: Alex ZOU, Innosail
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RISC-V Architecture Fusing Custom-Accelerator-As-Software
Ronald Hui
CTO
ViShare Technology Ltd.
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NEOX | GA100: Industry first RISC-V GPGPU for the MCU market
Xianggang Kong
Director of Business Development
Think Silicon S.A.
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High Performance RISC-V and Cache Coherence Interconnect IP solution
Zhiguo Ge
NoC chief architect
StarFive
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Demonstrating RISC-V Value in Fast Growing AI market
Rocky Zhang
Principal Field Application Engineer
Sifive, Inc.
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Break
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2:40 pm
Memory IP
Chairperson: Alex ZOU, Innosail
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Semiconductor IPs for Memory, Flash storage and wireless applications
Ravi Thummarukudy
CEO
Mobiveil Inc.
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LPDDR Support on Mature Technology Nodes
Minlin Fan
OPENEDGES Technology, Inc.
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Break
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3:40 pm
Interface IP
Chairperson: Alex ZOU, Innosail
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Interface IP: The Key Force Accelerating AI Chip Innovation and Performance Leap
Wang Shang-Yuan
Director of Product Marketing
AkroStar
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Interoperable SoC Framework to Overcome PCIe Design Verification Challenges
Queena Liu
Applications Engineering, Staff Engineer
Synopsys, Inc.
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SerDes + UCIe: The High-Speed Interface IP Solution for High-Performance Computing
Jerry Lyu
Senior FAE
eTopus Technology Inc.
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Wireless and Batteryless Interface for IoT
Alexander Kovalevsky
Chief Technical Officer
NTLab
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1:00 pm
Artificial Intelligence
Chairperson: Bulu Xu, SSIPEX
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IP Challenges in AI era
Dr. Bulu Xu
Vice Director
SSIPEX
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How Standards-Based Protocols are Imperative for the AI Workloads of Tomorrow
Arno Li
AE Director
Cadence Design Systems, Inc.
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Scalable, Flexible Edge AI accelerator: Silicon-Proven IP for Consumer Electronics
ChangSoo Kim
CEO
AiM Future, Inc.
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Meeting the Needs of AI Training with HBM3E
AI training models are growing in both size and sophistication at a lightning pace, requiring greater and greater bandwidth. With its unique 2.5D/3D architecture, HBM3E can deliver Terabytes per second of bandwidth. Join Rambus to hear how HBM3E meet s the memory needs of state-of-the-art AI training models.  ... 
Kai Zhao
Senior Principal Engineer in Field Application Engineering
Rambus, Inc.
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DSS for AI: Rapidly design Flexible, configurable Heterogeneous SoCs
Leon Zhang
R&D VP
ChipEasy
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Break
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3:00 pm
Automotive and Security Solution
Chairperson: Bulu Xu, SSIPEX
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Automotive HSM - Solve the ISO/SAE 21434 Cybersecurity Challenge & Set the Stage for Quantum Safety
Yaqiang Pei
Senior Staff Application Engineer
Synopsys, Inc.
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Quantum Safe Cryptography: Protecting Devices and Data in the Quantum Era
Quantum computers will eventually become powerful enough to break current asymmetric encryption, placing important data and assets at risk. In this presentation, Rambus will discuss recent developments in Quantum Safe Cryptography and highlight what you need to know to protect devices and data in the quantum computing era. ...
Kevin Zhang
SPE FAE, Rambus
Rambus, Inc.
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Security From Chip-To-Cloud with PQC (Post Quantum Cryptography)
Shengnan WANG
General Manager China
Secure-IC
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Break
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4:20 pm
Video IP
Chairperson: Bulu Xu, SSIPEX
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Versatile Video Coding (VVC) Codec Update and Market Adoption
Yujing Wei
VP, APAC Business Development
Allegro DVT
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Advanced AI-Driven Image Signal Processing for Next-Gen Camera
Fangbing Yue
Director of ISP IP
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
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