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Systematic Verification Framework for Memory Subsystem Ensuring Reliability and Robustness
Pratibha Sukhija - Senior Product Management and Marketing Manager - Cadence Design Systems, Inc.
Biography :
| Pratibha is the Senior Product Management and Marketing Manager for Verification IPs and Memory Models at Cadence Design Systems Pratibha is responsible for all the company's Verification IP and Memory Model portfolio management. She plays a key role in the continued development of client partner relationships, ensuring flexibility in response to an increasingly demanding marketplace. Pratibha spent 17 years in EDA, and services industry with deep knowledge of the chip production cycle through working experience with customers in roles like Application Engineering, Sales, Account Management, Business Management at Synopsys, Mentor Graphics, Capgemini. Pratibha earned Post Graduate Dip in VLSI and an Honors degree in Bachelor of Technology- Electronics from Kurukshetra University, India |
Dinesha Rao - Senior Architect - Cadence Design Systems, Inc.
Biography :
| Dinesha Rao is a Senior Architect at Cadence Design System and manages Memory Model, DFI Memory Controller and PHY Verification IPs. Dinesha led the development of Denali memory models starting with LPDDR memory models. He was also responsible for developing HBM and GDDR VIPs. He also headed a team which developed reusable library components for Verification IPs. At Cadence, Dinesha has made major contributions in shaping the system performance modelling solutions. Additionally, he manages DFI Memory Controller and PHY Verification IPs which provides a complete memory verification solution. Dinesha is an EDA industry veteran with 22 years of extensive experience in software architecture and modelling. Prior to joining Cadence, Dinesha spent 10 years at Synopsys where he worked on state of art RTL synthesis solution. Dinesha earned Computer Engineer degree from National Institute of Technology, Surathkal, India |
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