When : April 25th, 2024
Where: Hyatt Regency Santa Clara
5101 Great America Parkway, Santa Clara, CA
Join D&R IP SoC Silicon Valley 24 !! A worldwide connected Event !!
A worldwide connected Event !!
D&R IP-SoC Silicon Valley 2024 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems.
IP-SoC providers, the seed of innovation in Electronic Industry, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry.
IP consumers can view at a glance the latest Technology trends and exciting Innovative IP/SoC products. Through a global view, Electronic systems leaders may identify disruptive innovation leading to new market segment growth.
Any question? Please contact us
|
-
To join the event, you need to be registered.
If not yet done, Register Now !
|
|
9.00 am
Welcome
|
|
|
IP providers: the "Human" Intelligence in the semi conductor world
Gabrièle Saucier
CEO
Design And Reuse
|
|
|
9.30 am
Artificial Intelligence
Chairperson: Geir Eide - Siemens EDA
|
|
|
Implementing Transformer Neural Networks for Visual Perception on Embedded Devices
Abstract: This paper examines the complexities surrounding the integration of transformer models onto embedded devices. Transformers are a class of neural network models originally designed for Nature Language Processing (NLP). For visual perception , transformers have emerged as a powerful tool due to their exceptional ability to model long-range dependencies in images and process multi-modal data. Resource constraints form a central challenge when we attempt to deploy transformers on embedded platforms. Transformers demand substantial memory for parameter storage and intermediate computations due to their self-attention mechanisms. Embedded devices, characterized by limited memory capacity and bandwidth, struggle to accommodate these requirements. Furthermore, the intricate computations involved in self-attention hinder real-time inference on devices with modest processing capabilities. Energy efficiency, essential for prolonged device operation, adds another layer of complexity, demanding optimal model architectures. Mitigating these challenges demands a multifaceted approach. Optimization techniques like quantization, which reduces numerical precision of model parameters, ameliorate memory constraints. Pruning and sparsity techniques, removing less critical connections, alleviate computation demands. Knowledge distillation or other transformer architecture optimization techniques transfer the knowledge from larger models to compact yet accurate models. In the paper we also discuss hardware accelerators like NPU customized for transformer workloads, and software techniques efficiently mapping optimized transformer models to hardware accelerators.  ... 
Shang-Hung Lin
PhD, VP of Neural Processing Products (NPU)
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
|
|
|
Neuromorphic Processor IP for a New Generation of SoCs featuring Temporal Event-based Neural Networks (TENNs)
This presentation highlights the benefits of Temporal Event-based Neural Networks (TENNs), a patent-pending innovation introduced in the Akida 2.0 neuromorphic processor IP developed by BrainChip. TENNs combine spatial and temporal convolutions to pr ocess sequential data, excelling at processing temporal data at the edge much more efficiently than traditional RNNs. ...
Steve Thorne
Vice President of Sales
BrainChip Inc.
|
|
|
Meeting the Needs of AI Training with HBM3E
AI training models are growing in both size and sophistication at a lightning pace, requiring greater and greater bandwidth. With its unique 2.5D/3D architecture, HBM3E can deliver Terabytes per second of bandwidth. Join Rambus to hear how HBM3E meet s the memory needs of state-of-the-art AI training models. ...
Johnny Kim
Senior Principal Engineer
Rambus, Inc.
|
|
11.00 am
Artificial Intelligence - 2
Chairperson: Jeff Galloway - Silicon Creations
|
|
|
How IP will Enable Low-Power AI
Ron Lowman
Strategic Marketing Manager
Synopsys, Inc.
|
|
|
Advancing AI Connectivity through Linear Pluggable Optics Driven by High Performance SerDes
The rapid evolution of Artificial Intelligence (AI) has propelled the demand for efficient and high-speed connectivity solutions to enable seamless data transmission within AI-driven systems. Linear pluggable optics (LPO) have emerged as a transforma tive technology, revolutionizing AI connectivity by addressing key challenges associated with high-speed data rates - reach, latency, energy efficiency and scalability. Linear pluggable optics are optical transceivers without a CDR or DSP, lowering the power and latency associated with a DSP providing energy efficiency of to AI connectivity. By optimizing power consumption without compromising performance, still meeting the operating requirements of 100GbE links, these optics contribute to the overall sustainability of AI infrastructure. This is particularly relevant as the environmental impact of large-scale AI deployments becomes a focal point in technological development. This presentation will go over the fundamentals of LPO’s, and how Alphawave Semi SerDes IP is enabling this technology for (not so) future deployments. ...
Michael Klempa
Product Marketing Specialist
Alphawave Semi
|
|
|
How Gen-AI will reshape the world of semiconductor IP
Using Generative-AI for software development has been all the hype lately. But what about using it for hardware development? And what about using it more specifically for the way we design, use and integrate IP? In this presentation, I will give an update on the latest developments in this respect. ...
Hans Bouwmeester
VP Sales
PrimisAI
|
|
|
Shooting through the Semiconductor Datasheets - Generative AI
Semiconductor companies are leveraging Generative AI for superior customer experience. While the semiconductor industry dabbles with solving complex problems like writing bullet proof verified hardware design language, this solution addresses product recommendations, evaluation, and integration to e-commerce & other Saas based platforms for effective tracking and sales. The human-like customer experience solution keeps learning and provisioning for questions that are out of realms of the solution. Though there are challenges to be addressed largely from security and confidentiality. Overall, tunning well with the philosophy of continuous improvement while reducing the cost, is it becoming a must have implementation. ...
Eklovya Sharma
Director of Sales
Cyient Inc
|
|
1.00 pm
Processor IP
Chairperson: Ravi Thummarukudy - Mobiveil Inc.
|
|
|
Addressing Tomorrow's Automotive Compute Needs with Cadence
Over the years, the amount of compute required by vehicles for ADAS and driverless applications has go up several magnitudes. And feeding this compute requirement requires processing enormous amounts of cameras, radars, lidars and sensor data. In the past, specialized and discrete processors were used to handle image, radar and lidar data independently. However, these requirements have since evolved and the need for a singular and unified processor has become apparent. Aside from the classical approaches, AI is now also becoming prevalent for radar and sensor fusion applications. In this presentation, we plan to cover Tensilica's answer for such requirements. ...
Pulin Desai
Cadence Design Systems, Inc.
|
|
|
Overview of the Quadric GPNPU (general purpose NPU)
Steve Roddy
CMO
Quadric
|
|
|
|
Accelerating RISC-V Innovation in Automotive, AIoT & Consumer Markets
Rich Collins
Director of Product Management
Synopsys, Inc.
|
|
Video IP
|
|
|
Video IP's Role in Multimedia Application and Use-cases
Andy Lee
Vice President, US Marketing
Chips&Media, Inc.
|
|
2.45 pm
Security Solution
Chairperson: John Swanson - Synopsys, Inc.
|
|
|
|
Quantum Safe Cryptography: Protecting Devices and Data in the Quantum Era
Quantum computers will eventually become powerful enough to break current asymmetric encryption, placing important data and assets at risk. In this presentation, Rambus will discuss recent developments in Quantum Safe Cryptography and highlight what you need to know to protect devices and data in the quantum computing era. ...
Adiel Bahrouch
Director of Business Development
Rambus, Inc.
|
|
|
AI-powered cybersecurity: Securyzr™ Intrusion Detection System (IDS)
Secure-IC’s Intrusion Detection System (IDS) enhances protection against potential intrusions by leveraging Securyzr™ integrated Secure Element (iSE) S700 Series, and in particular data and alarms supplied by dedicated anti-tampering IPs, s uch as Active Shield and Digital Sensor, embedded within iSE S700. Discover on this presentation how Securyzr™ IDS monitors CPU, memory, network traffic, device components, and sensors, employing AI to discern threats and update models seamlessly. ...
Yathiendra Vunnam
Field Application Engineer
Secure-IC
|
|
|
|
Addressing High-Performance Data Center Bandwidth & Security Challenges
John Swanson
Senior Product Line Manager
Synopsys, Inc.
|
|
|
Embracing Security: A Comprehensive 360-Degree Approach
Lamyae Lahlou
Product Manager
Kudelski IoT
|
|
|
|
9.30 am
Chiplet Solutions
Chairperson: Kalar Rajendiran - Confera Corp.
|
|
|
|
UCIe Progress Report: Big Enhancements, IP Maturity, and Ecosystem Interoperability
Manmeet Walia
Sr. Director, Product Management
Synopsys, Inc.
|
|
|
Mixed Chiplet systems with wide range of nodes is becoming real
As the optimum node for cost can easily range from 7nm to 40nm it is critical that Chiplet interfaces support these nodes. We discuss the barriers and update solutions to enable broad use of Chiplets for cost sensitive markets.
Kash Johal
CEO
YorChip
|
|
|
Chiplet-Based Compressed LLC Cache & Memory Expansion IP Solutions
HBM memory chiplets, Non volatile memory chiplets, DDR memory over CXL and LLC cache chiplets help mitigate the infamous memory and SRAM scaling walls that limit compute performance in data centers and smart devices. However, chiplet based memory/ ca che Total Cost of Ownership(TCO) currently limits deployment at hyperscale. A new hardware accelerated chiplet IP that compresses memory 2-4X in real time, at CACHE LINE granularities with sub 10ns latency can be integrated with SRAM LLC (Last Level Cache) chiplets, Nonvolatile memory chiplets and CXL connected memory chiplets, making the TCO more cost effective in terms of $$/GB without compromising performance. While this capability by itself is compelling, When coupled with a high speed coherent mesh network and protocol that can interconnect within an SoC, link independent processors into a chiplet and connect processor with main memory and I/O, tremendous return-on-investment and flexibility and efficiency in managing resources can be achieved. In this presentation, we detail out the Architectural building blocks that integrate with existing chiplet ecosystem components and have the potential to lower the memory and LLC cache chiplet adoption barrier for large memory applications in the Cloud, Hyperscale and Automotive segments. Product details: https://www.zeropoint-tech.com/news/zeropoint-ip-offerings-updated-overview-released ...
Jack Guedj
CEO
Numem
|
|
11.00 am
Chiplet Solutions - 2
Chairperson: Daniel Nenni - SemiWiki
|
|
|
On-Die Power Management for SoCs and Chiplets
Rounak Lokare
Senior Circuit Design Engineer
Analog Bits Inc.
|
|
|
Optimized clocking solutions for high performance die-to-die interfaces
Blake Gray
Director of Hardware Engineering
Silicon Creations
|
|
|
|
AI System Connectivity for UCIe and Chiplet Interfaces Demand Escalating Bandwidth Needs
In the dynamic and evolving landscape of artificial intelligence (AI) systems, the exponential demand for high bandwidth is becoming more challenging. This abstract explores the interoperable integration of UCIe and chiplet interfaces to address the growing needs of AI architecture. In an effort to support the future growth of the chiplet connectivity ecosystem, the increased throughput of UCIe to enhance chiplet data transfer rates and to optimize energy efficiency paves the way for advancements in AI system performance. In parallel, concurrent advancements in memory, PCIe/CXL, and other high speed interface protocols consistently escalate data rates to keep up with the pace of increasing bandwidth requirements. UCIe and chiplet interfaces aligns with the broader trend of escalating data rates across key system components. Chiplets are reliant on upcoming architectures and new solutions for the ability to provide unique connectivity per application specific needs. By integrating these advancements together, a complete chiplet solution can address the bandwidth needs of next-generation AI systems. ...
Letizia Giuliano
VP, IP Product Marketing & Management
Alphawave Semi
|
|
|
High Performance UCIe Chiplet and Memory Subsystems IPs Optimized to Turbo Charge Next Gen AI SOC (Covering Chiplet/GDDR7/LPDDR5X/HBM3E up to 3nm)
Gordon Ao
CEO
Innosilicon
|
|
1.00 pm
Design Challenges
Chairperson: Mahesh Tirupattur - Analog Bits Inc.
|
|
|
Implementing Safe Coherent Networks-on-Chips for Automotive ADAS Applications
Guillaume Boillet
Sr. Director Strategic Marketing
Arteris IP
|
|
|
Smallest, ultra-low leakage, ultra-low capacitance ESD protection
Reduced total ESD area (50% smaller) Lower parasitic capacitance for high-speed interfaces (30% to 50% lower capacitance) Lower leakage for wireless or sensor interfaces (nA) Higher ESD robustness for automotive, industrial applications (>8kV HBM) Higher voltage tolerance (5V pad) Sofics has proven solutions on every node down to 3nm ...
Bart Keppens
Chief Business Development
Sofics
|
|
|
MIPI CSI-2 in Low-Power Image Sensors for Industrial and Consumer IoT Applications
Justin Susumu Endo
Mixel, Inc.
|
with Brian Lenkowski
ams OSRAM
|
|
|
|
2.15 pm
Monitoring Solution
Chairperson: Randy Fish - Synopsys, Inc.
|
|
|
|
The Critical Role of Embedded Monitor IP in Enabling Silicon Lifecycle Management Use Cases
Ash Patel
Director of Product Management
Synopsys, Inc.
|
|
|
Boost SoC debug with smart monitors and embedded software
On-chip functional monitors can dramatically simplify debug and optimization of complex SoCs. This presentation will explain how to use embedded software running on the target silicon to extract even more insight from such monitors, enabling for inst ance real-time non-intrusive logging and performance analysis. ...
Geir Eide
Director, Product Management
Siemens EDA
|
|
3.00 pm
Verification and test challenges
|
|
|
|
Systematic Verification Framework for Memory Subsystem Ensuring Reliability and Robustness
Memory subsystem is a critical component in modern computer systems, and its design and verification are challenging tasks. "SVRAND - Randomization" and "Auto Configuration" solutions are the framework for a Systematic Memory Subsystem Verification e nsuring Reliability and Robustness. Leveraging these practices can help designers differentiate, optimize, and accelerate verification cycle. ...
Pratibha Sukhija
Cadence Design Systems, Inc.
|
with Dinesha Rao
|
|
|
|
|
Automatic generation of Device Driver and Programmer's Reference Manual from PSS
Freddy Nunez
Application Engineer
Agnisys, Inc.
|
|
3.45 pm
eFPGA
Chairperson: Mike Li - Corigine Inc.
|
|
|
Elevate your SoC - Customer eFPGA Use Cases for Adding Adaptability and Acceleration
Jayson Bethurem
VP Marketing
Flex Logix Technologies, Inc.
|
|
|
Drive and Fly with Time Critical Networking and Embedded FPGA
Chinh Le
LeWiz Communications, Inc.
|
|
|
|
|
Partner with us
|
|
List your Products
Suppliers, list and add your products for free.
| |
© 2024 Design And Reuse
All Rights Reserved.
No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse.
|
|
This website uses cookies to store information on your computer/device.
By continuing to use our site, you consent to our cookies.
Please see our Privacy Policy to learn more about how we use cookies and how to change your settings if you do not want cookies on your computer/device.
| |
Home
Contact Us
Partnership Offers