When : December 4th - 5th, 2023
Where: Hôtel EUROPOLE, 29 rue Pierre-Sémard - Grenoble, France
Join D&R IP SoC Conference 23 !! A worldwide connected Event !!
A worldwide connected Event !!
IP-SoC 2023 will be the 26th edition of the working conference fully dedicated to IP (Silicon Intellectual Property) and IP based electronic systems.
The event is the annual opportunity for IP providers and IP consumers to share information about technology trends, innovative IP SoC products, Breaking IP/SoC News, Market evolution and more.
The Grenoble event is a special event as it is also the annual IP Think Tank meeting where high level executives, market analyzer and technical experts from Foundry/technology, to new applications share their vision about the future of the IP concept. It will be the right time to analyze the fast evolution and consolidation in the IP market and IP business.
As far as the application domains are concerned it is important to give high to new application domains and take into account new system requirements such as 3D packaging, Security, Artificial Intelligence, Green Electronics, ...
And over all you cannot miss The wine Tasting Party !!
Exhibition tables and "discussion panels" will favor vendor and customer meetings.
Any question? Please contact us
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To join the event, you need to be registered.
If not yet done, Register Now !
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9.00 am
Introduction Session
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Welcome : Innovation in semi conductor industry
Gabrièle Saucier
CEO
D&R
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Empowering Innovation in the Age of Custom Silicon
Industry leaders in data center, AI, high performance computing and networking are increasingly demanding custom silicon solutions to deliver the specialized processing they need. Arm Neoverse was created specifically to deliver the industry leading performance efficiency and unmatched design flexibility to enable this transformation. This talk will cover the latest additions to the Neoverse story: Arm Neoverse CSS delivers a fully validated, pre-integrated RTL implementation of a multi-core Neoverse compute complex; Arm Total Design assembles an ecosystem committed to frictionless delivery of custom SoCs based on Neoverse CSS, with support from industry leaders at every stage of semiconductor design and manufacture. The path to innovative, custom silicon for the age of AI has never been faster.  ... 
Eric Lalardie
Director
Arm Ltd.
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Break
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10.00 am
New technology the lead of innovation
Chairperson: Yves Quere - CEA
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Greening the Road Ahead: Revolutionizing the Automotive Industry with FD SOI Technology
Philippe Flatresse
Product Marketing
SOITEC
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Technologies enabling future mobile connectivity & sensing
Francois Brunier
Partnership Program Manager
SOITEC
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Digital Beamforming design in mmW: A 22nm FDSOI transceiver practical case
Facing a saturated conventional radiofrequency range, developing mmWave Beamforming architectures has become mainstream in RFIC design. Moreover, pure digital Beamforming is the best strategy to address dense end-user area. However, this architecture comes with its own challenges. In this presentation, we will discuss how they have been addressed in the development of a fully integrated transceiver solution operating at 39 GHz. ...
Jérôme Prouvée
Layout Engineer & Project Manager
CEA
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Break
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11.20 am
Artificial Intelligence IP and SoC
Chairperson: Costas Conistis - Alphawave Semi
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Meeting the Needs of AI Training with HBM3
AI training models are growing in both size and sophistication at a lightning pace, requiring more and more bandwidth. With its unique 2.5D/3D architecture, HBM3 can deliver Terabytes per second of bandwidth. Join Philip Van Den Heuvel to hear how HB M3 meets the memory needs of state-of-the-art AI training models. ...
Philip Van Den Heuvel
Regional Sales Manager
Rambus, Inc.
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Innovative Integrated IP SoC Design for Edge AI
In today’s world, we are all generating digital data whether we are at home, at work or on the move. We expect that data to be processed securely and for the corresponding decision inferences to be made autonomously and instantly. End-user e xpectations demand a new perspective on Artificial Intelligence (AI) and its application at the edge where data gets generated. Bandwidth and reliable connections are expensive. Once the data is transmitted it may no longer be secure. Energy consumption must factor into sustainability goals. Taken together, it is expected that inferences be made by the device at the edge and real-time decisions to be made autonomously to enhance the user experience in an economically viable manner. These market requirements dramatically increase complexity of the system-on-chip (SoC) at the heart of the Edge AI device. The SoC designer must balance many factors to deliver an economically viable chip: • Unsatiable demand for more general-purpose compute • The need for AI compute • Lower costs, latency and energy (to meet sustainability goals) • Always-on connectivity • Compliance with national standards to keep us safe as citizens and keep our data secure • Developer experience The industry has converged on the need for heterogenous compute to satisfy these use cases. Multiple different compute entities matched to dedicated tasks while offering a coherent system to the software developer. The days of one single high-performance CPU are gone. We are committed to the movement of AI to the edge and for deployment at scale, so this presentation will showcase Arm Corstone IoT Solutions portfolio, a series of subsystems where several compute engines are integrated in an optimal manner to deliver a solution for Edge AI use cases across many verticals. The presentation will describe the benefits of the subsystem to the SoC designer and how to generate unique products out of it. Join this talk to hear more about: • Corstone subsystem IP • Building up Corstone into an SoC • Adding third-party IP into Corstone • Running workloads on Corstone ...
Tim Menasveta
Director of IoT Product Management
Arm Ltd.
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Transforming Far-Edge Computer Vision with Energy-Efficient A
Vincent Huard
Chief Technology Officer
Dolphin Semiconductor
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Lunch
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1.30 pm
New Challenges
Chairperson: Eric Lalardie - Arm
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The Lossless Compression Challenge: from Networking to Data centers
Lossless compression offers space-saving benefits without compromising data integrity. It optimizes memory usage and reduces bandwidth requirements. It can be used to reduce accesses to off-chip memories and therefore increase efficiency and reduce p ower consumption. We will present the CAST portfolio of lossless data compression cores and our roadmap for the future. ...
Dr. Calliope-Louisa Sotiropoulou
Sales Engineer
CAST, Inc.
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Addressing connectivity scalability in the AI world with Mulit-Standard IO Chiplets driving next generation interconnects
This presentation will touch on the evolution towards 1.6T technologies, and how standards bodies are addressing form factors and high speed signaling to achieve scalable and interoperable PCIe, CXL and Ethernet solutions. We will touch on potential mediums and bandwidth requirements of the application channels, and potential generations of optical technologies, from pluggable optics, to on board or near packaged, to ultimately 2.5D co-packaged optics. We will also talk about the biggest challenges for making 1.6T mainstream and how 200G-DSP-based SerDes transceivers leveraging CMOS scaling, interconnect technology, can succeed. ...
Michael Klempa
Product Marking Specialist
Alphawave Semi
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Break
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2.30 pm
Safety Critical Applications
Chairperson: Dr. Calliope-Louisa Sotiropoulou - CAST
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IP Core Considerations for Ensuring Functional Safety in Safety-Critical Applications
For many years, IP cores have been used to accelerate the development of electronic circuits. Beyond making IC design more efficient overall, incorporating a component that has already proven itself in use can reduce the risk of missed tapeout target s, late product launches, and substantial associated costs. Though the benefits of IP for expediting chip design are well documented, engineers must take many factors into account when selecting these predefined circuit parts. It is vital to clarify, among other parameters, whether the IP core is "silicon-proven," whether the area utilization corresponds to the defined specifications, and whether the power consumption makes the use viable. The quality of the IP core is of particular importance if it destined for use in a safety-critical application, such as automotive, aerospace, or military and defense. When incorporating IP into complex circuits such as these, chip designers must take steps to ensure that certification and compliance with industry safety standards, such as ISO 26262 or DO-254, is attainable. In this presentation, SmartDV presents a thorough overview of the detailed considerations that chip design teams should bear in mind when sourcing third-party IP to meet their functional safety (FuSa) goals. ...
Philipp Jacobsohn
Senior Staff Applications Engineer
SmartDV Technologies
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GRLIB: VHDL IP library for fault-tolerant SoC
Fabio Malatesta
Product Marketing Engineer
Frontgrade Gaisler
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3.10 pm
Automotive Applications
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CAN XL - can safety go in hand with performance?
Jacek Hanke
CEO
Digital Core Design
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Solve the Latest ISO 21434 Cybersecurity Challenge with an Automotive HSM
Ruud Derwig
Senior Staff Engineer for Security IP
Synopsys, Inc.
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Break
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4.20 pm
Security Solutions
Chairperson: Bart Stevens - Rambus, Inc.
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Which IP for Which Security Certification Standard,
Finding certified secure solutions at the chip design stage facilitates up-front integration and production. Common Criteria and SESIP certifications are the current international ‘gold standards’ for embedded system security. This presenta tion highlights the benefits of each kind of certification, enabling SoC manufacturers to choose the right level for their IP. ...
Ludovic Merrien
Security Certification Leader
Tiempo Secure
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LDPC Encoder/Decoder
LDPC Encoder/Decoder for 5G, DVBS2, WiMax, 802.11n etc... applications High-performance implementation using a sum-product algorithm, which converges faster with fewer iterations. The encoder is an XOR tree to calculate the parity bits. The encode r is fixed for a particular application. The Encoder/Decoder is generated explicitly for a specific generation of parity matrix. The Encoder/Decoder is generated from the Alist file, which is generically generated for any application. The decoder can do iterations in less than five cycles with 8 to 10 iterations in a typical case. ...
Manish Mahajan
Founder
Secantec, Inc.
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Security from chip to cloud with PQC (Post-Quantum Cryptography)
To ensure end-to-end cybersecurity, controlling the product lifecycle and security is crucial. Secure-IC provides a comprehensive solution covering IC design, certification, manufacturing, deployment, and decommissioning. This approach, coupled with a scalable Secure Element on Embedded Edge devices, enhances connected device lifecycle management. Additionally, the rise of Post-Quantum Cryptography presents new challenges, which Secure-IC aims to address with a holistic Chip-to-Cloud security solution. ...
Brice Gaignoux
EMEA Pre-Sales Engineer
Secure-IC
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Break
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5.40 pm
Security Solutions - 2
Chairperson: Ruud Derwig - Synopsys, Inc.
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Quantum Safe Cryptography: Protecting Devices and Data in the Quantum Era
Quantum computers will eventually become powerful enough to break current asymmetric encryption, placing important data and assets at risk. In this presentation, Bart Stevens will discuss recent developments in Quantum Safe Cryptography and highlight what you need to know to protect devices and data in the quantum computing era. ...
Bart Stevens
Senior Director of Product Marketing
Rambus, Inc.
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How will platform and communication security evolve in the quantum computing era?
What changes will be required to address the quantum computing threat to existing Cryptography standards that underpin platform and communication security. PQShield is working on developing IP solutions for the Post Quantum Cryptography Era.
Graeme Hickey
VP Engineering
PQShield
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The Power of Physical Unclonable Functions (PUFs)
Chris Jones
Director, Field Application
Crypto Quantique
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9.00 am
Processor IP
Chairperson: Philippe Quinio - STMicroelectronics
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Beyond one-size-fits-all: The power of tailored CPUs
Now that Moore’s Law has stalled, innovative approaches are required to make sure that companies can successfully differentiate their products. One increasingly popular approach is to use Custom Compute to enable extraordinary efficiency gains i n processing elements, but it is very complex to do by hand. Codasip enables automation of Custom Compute, thanks to a very efficient methodology, and its latest family of customizable processors can bootstrap the development of a new class of products. This new offering will transform the way SoC architects will be able to optimize systems. ...
Mike Eftimakis
VP Strategy & Ecosystem
Codasip GmbH
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Survey of market available processor IP
Dagmara Zielinska
Partnership Program Manager
D&R
with Gabrièle Saucier
CEO
D&R
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9.40 - 11.00 am
From Processor IP to Processor or supercomputer chip:
What is needed and what is the next success track ?
This panel gives an opportunity to exchange some vision about the future of processor IP up to extension to processor / multiprocessor chip.
With the participation of:
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Fabio Malatesta - Product Marketing Engineer - Frontgrade Gaisler
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Mike Eftimakis - VP Strategy and Ecosystem - Codasip GmbH
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Loic Lietar - Co-Founder & CEO - GreenWaves Technologies
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Thierry Lelégard - Head of Platform Security - SiPearl
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Break
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11.30 am
Analog IP
Chairperson: Philippe Flatresse - SOITEC
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Adaptive Voltage Scaling (AVS): Enhancing Chip Efficiency
Vincent Telandro
Product Marketing manager (Power Management IP)
Dolphin Semiconductor
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Technology Analysis: what you need to know before embarking on analog design migration
The successful migration of analog & mixed signal IPs can be impacted by a number of variables: device performance in target and source process technologies, migration costs, and device availability, to name just a few. Knowing what challenges might occur during migration, before migration takes place, is critical to its success. By performing an in-depth analysis of the two technologies involved using AMALIA Technology Analyzer, decision makers can fully understand the impact upfront, enabling designers to optimally organize the migration effort. ...
Jean-François Lambert
Director of Business Development
Thalia
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Lunch
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1.20 pm
Design Platform
Chairperson: Philippe Flatresse - SOITEC
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Hybrid Cloud Management for IP Development
Sundar M
Director
Tessolve Semiconductor Private Limited
with Pitchumani Guruswamy
Tessolve Semiconductor Private Limited
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Online Only
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A novel approach for SoC design resource management and prediction
Chouki Aktouf
Co-Founder
Innova Advanced Technologies
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Multi-IO co-processor with TSN
Vincent Laporte
CTO - V.P. BU
CetraC
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Break
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2.30 pm
Verification Platform
Chairperson: Patrick Blouet
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IP QA Best Practices
Lionel Couder
Sr. Applications Engineer
Siemens Digital Industries Software
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Important Considerations for Verification of CXL Devices
INTRODUCTION Compute Link Express (CXL) is break-through technology for modern day compute requirements driven by high-performance computing, cloud, AI and ML. Having CXL being rapidly adopted by big industry players in processing and storage land scape, brings multi-fold verification challenges from IP to System level. In this paper, we will discuss these verification challenges and important considerations that should be adopted to significantly mitigate these challenges. CXL.IO PATH VERIFICATION CXL.io largely is similar to PCIe link. Typical ‘Hello world’ testcase for CXL devices would be link-up in CXL mode using Alternate Protocol(AP) negotiation, Virtual channel(VC) credit initialization on CXL.io data link layer and enumeration of PCIe, CXL defined configuration space capabilities and control registers being successful. This would guarantee PCIe protocol stack is functional as in PCIe mode of operation. Additionally, it would be crucial to make sure that CXL compliant devices truly falls-back in PCIe mode if Alternate Protocol(AP) negotiation fails. VALIDATING CACHE MODELLING CXL.cache is developed to allow Devices to access and cache Host attached memory. CXL.cache works on MESI (Modified, Exclusive, Shared, Invalid) coherence protocol. And, by principle link is developed as an asymmetric link which means that Home Agent (dealing with cache coherency resolution) is required to be implemented only in CXL Host. Below example illustrates how CXL link maintains coherence in Type1 devices with only Host Memory cacheable by both Host and Device. Multiple such operations need to be performed at 4KB page boundary for typical workload. Flows become complex with multiple request/response transactions for one operation when Device Memory is also visible to the system and is cacheable by both CXL Host and Device for Type2 CXL devices. Unit level testcases emulating various buried cache states and covering all flows should be included in verification plan. EFFICIENT PACKING OF TRANSACTION LAYER PACKETS AT LINK LAYER CXL specification for CXL.cachemem layer divides FLITs into various slots to efficiently pack transaction layer packets. Sophisticated algorithms catering to different combinations of traffics from cache, mem semantics need to be devised to make sure CXL link is operating on maximum throughout. Highly randomized testcases with varied traffic profiles is must to expose both functional and performance related packing bugs. Below example illustrates typical request response packing at link layer. MULTIPLEXING IO AND CACHE MEM DATA CXL introduces arbitration and multiplexing layer to multiplex traffic from CXL.io and CXl.cachemem blocks. Post IP bring-up phase (which would have CXL.io traffic), right balance of CXL.cahemem and CXL.io weights have to be maintained. Workload aware algorithms could highly optimize the traffic going on physical layer. For example, during intensive cache operations CXL.io would be put on lower weights while for interrupt execution CXl.cachemem flows would be put on lower weightage. Validating IP for such scenarios reduces the verification cycle when integrated at sub-system level. In parallel, need to ensure crucial packets such that UpdateFC, LLCRD are not blocked while setting different weights. SECURITY ASPECTS – INTEGRITY AND DATA ENCRYPTION (IDE) CXL based applications when transmitting mission-critical workloads incorporate Integrity and Data Encryption(IDE) capability. CXL.io follows IDE flow as mentioned in PCIe, CXL.cachemem does have considerable variations from PCIe flow. Introduction of IDE module on CXL.cachemem brings complexity with AES-GSM algorithm, MAC generation, reception, authentication key programming and exchange mechanism, key toggle, plaintext CRC (PCRC), etc. Notably, having the first testcase up with Memory Read/Write transaction on CXL.io and CXl.cachemem with IDE enabled itself is a major milestone from a verification standpoint. And then advancing to test scenarios containing large numbers of packets exercising various delays, surpassing numerous Epoch windows with sandwiched control FLITs would be a gradual effort. Post verifying functional correctness of IDE encrypted link, verification engineers should consider exercising long running testcases to ensure there no alarming performance dips. Skid IDE mode, by design, should have a lower penalty on latency and bandwidth numbers than containment IDE mode. Skid IDE mode does allow near-zero latency overhead. Containment IDE mode latency is added due to the requirement of ensuring MAC integrity before releasing the FLITs for further processing. Skid IDE mode guarantees better bandwidth utilization as MAC is transmitted after 128 FLITs, while for containment IDE mode, MAC is transmitted for every 5 FLITs. SYSTEM LEVEL DATA SCORE-BOARDING Certain bugs related to memory interleaving, address translation, packet byte enables, cache coherency may not be identified at IP level. Connecting protocol agnostic system level scoreboard across communicating nodes becomes a powerful debug aid for data integrity, coherency testing for interconnect-based design. PERFORMANCE BENCHMARKING CXL by design is a low latency and high bandwidth protocol. To ensure execute, cache, memory sub-blocks when integrated at system level take full advantage of CXL semantics, running stress testcases with numerous back-to-back system stimulus is must before verification sign-off. Analyzing peak bandwidth utilization, performance bottlenecks and maximum outstanding transactions can be populated in tabular form, observing waveforms or more sophisticated graphs as shown below. CONCLUSION As established by now, verifying CXL compliant devices requires a robust and exhaustive approach since it introduces complexity from IP to System level. Verification considerations discussed in this paper would definitely boost confidence and help left-shift verification effort. ...
Nicolas Dai
Application Engineer Architect
Cadence Design Systems, Inc.
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3.10 pm
Monitoring Platform
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Chip Condition Monitoring and Performance Optimization. Process/Voltage/Temperature Detectors in ASIC Design Methodology.
Semiconductor development focuses on improving performance and reducing silicon area. This approach promotes the use of low-scale processes, but it leads to denser designs and silicon overheating. The PVT Detector presents a unique solution for monit oring individual die status at key points. ...
Vsevolod Sergeenko
RFID Team Leader
NTLab
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The Critical Role of Embedded Monitor IP in Enabling Silicon Lifecycle Management Use Cases
To keep pace with the ever-growing performance demands of cutting-edge applications like HPC and automotive, device and system complexity continues to increase. The emergence of multi-die technology has also compounded this complexity. To meet these demands, designers can optimize both the health and performance of their silicon by gathering meaningful data at each stage of the device lifecycle and from silicon to system that can provide actionable insights for intelligent decision making. Silicon Lifecycle Management (SLM) is built on a foundation of in-chip monitors IP, data analytics and design automation. Environmental, structural and functional monitors enable these actionable insights which can be leveraged from the early In-Design phase through to In-Ramp, In-Production and ultimately during In-Field operation. In this presentation we will explore how SLM IP monitors, EDA tools and methodologies are the driving force behind intelligent data collection, storage and analysis which enables popular SLM use cases such as Vmin Optimization, Adaptive Voltage Scaling (AVS), Silicon Model Correlation, Process Classification, Mission Profile Analytics, Predictive Maintenance and Remaining Useful Life (RUL). ...
Dan Alexandrescu
R&D Engineer
Synopsys, Inc.
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