When : November 30th - December 1st, 2022
Where: Hôtel EUROPOLE, 29 rue Pierre-Sémard - Grenoble, France
Join D&R IP SoC Conference 22 !! A worldwide connected Event !!
IP-SoC 2022 will be the 25th edition of the working conference fully dedicated to IP (Silicon Intellectual Property) and IP based electronic systems.
The event is the annual opportunity for IP providers and IP consumers to share information about technology trends, innovative IP SoC products, Breaking IP/SoC News, Market evolution and more.
The Grenoble event is a special event as it is also the annual IP Think Tank meeting where high level executives, market analyzer and technical experts in all the design track from Foundry, technology, design methodology, EDA tools share their vision about the future of the IP concept. It will be the right time to analyze the fast evolution and consolidation in the IP market and IP business.
And over all you cannot miss The wine Tasting Party and special banquet for D&R 25th Anniversary !!
Exhibition tables and "discussion panels" will favor vendor and customer meetings.
Any question? Please contact us
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To join the event, you need to be registered.
If not yet done, Register Now !
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This year will also be the celebration year of D&R 25th anniversary
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Thus in a welcome session, gurus from various IP business fields will deliver their vision about the past quarter of century of IP business and give their prediction about the trends for the next decade.
- Day 1 - November 30th
- Day 2 - December 1st
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Registration opens at 7 am
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8.30 am
Welcome
Chairperson: Gabrièle Saucier - Design And Reuse ( About me) |
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Gabrièle Saucier
CEO
Design And Reuse
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After 25 years what's new
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Dr. Yervant Zorian
Chief Architect and Fellow President of Synopsys Armenia
Synopsys, Inc.
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The role of IP/SOC in Silicon Lifecycle Management
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Mike Eftimakis
VP Strategy and Ecosystem
Codasip GmbH
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The processor revolution is brewing - it won't be like the past 25 years!
The past 25 years have seen an exponential growth of IP and a fantastic processor evolution, how can we predict what will happen during the next 25 years? Following the currently visible trends will give us some indications, but it is very likely tha t disruptions will happen: we can already foresee some of them and show that the processing revolution is brewing!  ... 
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Patrick Blouet
Collaborative Program Manager
STMicroelectronics
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Sustainability of the electronic industry : A major challenge and a mine of innovation
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Break
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10.30 am
SOI the "European Green Touch"
Chairperson: François Brunier - Soitec ( About me) |
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François Brunier
Partnership Program Manager
Soitec
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CHIPS ACT: How Europe wakes-up
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Daniel Saias
CEO
ASYGN
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BEYOND5 - Low power 5G access point
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Wojciech Debski
CTO
Silicon Radar GmbH
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BEYOND5 - Car Interior Radar for Advanced Life-Signs Detection
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Philippe Flatresse
Soitec
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FDSOI the EU technology for a green transition
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Erkan Isa
Group Manager
Fraunhofer-Gesellschaft
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OCEAN12 IP Factory: From Research to Silicon
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12.05 pm
Enjoy your Lunch Break, sit down with your client and rest in "Le Jardin"
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1 pm
Automotive Solution
Chairperson: Dr. Yervant Zorian - Synopsys, Inc. ( About me) |
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Bart Stevens
Senior Director of Product Marketing
Rambus, Inc.
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Securing Automotive Semiconductors in the New Centralized Car Architecture
Vehicle systems and the semiconductors used within them are some of the most complex electronics seen today. New use cases of semiconductors in automotive such as in-vehicle networks and vehicle to cloud connections lead to new architectures abandoni ng the unsecure ECU based network, by moving to architecture domain controllers and eventually to a central zonal architecture controlled by a vehicle server. Ensuring these systems are both functionally safe and secure from cyberattacks has become mission critical. Bart Stevens will present silicon IP solutions for securing automotive electronics equipped with ISO26262 certified functional safety mechanisms. ...
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Jacek Hanke
CEO
DCD-SEMI
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CAN ALL - secure & comprehensive solution (not only) for automotive
CAN ALL, as the name suggest is a brave new world (not only) for automotive. Well known standard evolves together with functional safety – being the same 21st century approach to system design. Even the best engineer makes mistakes. That's why the ISO 26262 standard has been introduced. The main goal is to mitigate risks (systematic failures and random hardware failures) by providing appropriate requirements and processes. But this is just the beginning... ...
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Philippe Borges
Sr Staff Applications Engineer
Synopsys, Inc.
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Automotive-Grade IP for Next-Generation Zonal Architectures
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Benjamin Weinhardt
Head of Business and Collaboration Office
Siliconally GmbH
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Safe Communication Technology for Automated Vehicles
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George Wall
Group Director of Product Marketing for the Tensilica IP
Cadence Design Systems, Inc.
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A Flexible Approach for Meeting Automotive Functional Safety and Security Requirements
The proliferation of smart sensors in automotive applications such as ADAS has driven the distribution of intelligence closer to the edge domain. The need for rapidly processing and enhancing incoming camera images or quickly resolving objects in a LiDAR image is driving growth in the processing requirements for automotive smart sensors and edge devices. Additionally, these edge devices, which often incorporate programmable elements in the form of classic control CPUs or high-throughput DSPs, must also meet stringent functional safety requirements such as those specified by ISO 26262. In one classic model for functional safety, the edge devices are protected against random faults to the ASIL-B level, while sending fault information to an ASIL-D certified centralized device that would be in charge of managing the safety goals for the entire subsystem. However, as intelligence in the edge grows, it is often necessary for these edge devices to manage their own safety requirements, thereby requiring ASIL-D level of protection from random faults. SOC vendors addressing this market would often need to develop two classes of devices, some certified to ASIL-B and others certified to ASIL-D. Additionally, these devices must also be secured from attacks by malicious entities. Cadence's Tensilica IP processors include CPUs and DSPs for automotive applications such as radar and LiDAR processing, camera and sensor image enhancement, ADAS, auto infotainment and sensor fusion. In this session, learn how Cadence Tensilica processors can be used to create a flexible, functionally safe subsystem that can meet either ASIL-B or ASIL-D requirements through the use of its FlexLock dual-core lockstep capability, while also addressing the need for increasing security at the hardware level. You will also learn how Tensilica processors can be uniquely tailored to the end user's application requirements, and how Cadence provides its users with an ASIL-D certified compiler toolchain for the development of functionally safe firmware to run on these smart devices. ...
Online Only
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2.30 pm
Artificial Intelligence
Chairperson: Andrea Battistella - Imagination Technologies Group Ltd. ( About me) |
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Vincent Huard
CTO
Dolphin Semiconductor
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Democratizing Energy Friendly Ambient Computing
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Ramses Valvekens
CSO & managing director
easics
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nearbAI: scalable neural network inference for ASICs in XR devices
The two major requirements for neural network inference for extended reality (XR) devices can be summarized by ultra-fast response times and ultra-low power. nearbAI is easics' solution for immediate visual, aural and other feedback based on sens ory inputs, which is a necessity for live augmentation of the human senses. Each nearbAI core is an efficient neural network inference engine. The L3-Optimizer technology enables the user to optimize the solution in terms of area, power and performance. Our proof of concept implements live face detection on the Kria KV260 FPGA board with an inference time of 5ms with core running at 200MHz. ASIC synthesis using TSMC 22nm ULP technology for a medium core - 512 MACs - infers in 3.6ms at 300 MHz and consumes an average of 140 mW, with peak power at 280 mW. (Average power is estimated to be 20-30 mW when using TSMC 5 nm technology). The inference time for the medium core running at 600MHz is 1.7ms. The solution is integrated with Rokid glasses to demonstrate nearbAI's potential.- ...
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Break
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3.30 pm
RISC-V
Chairperson: Arnaud Wenzel - STMicroelectronics ( About me) |
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Florian Wohlrab
Head of Sales EMEA & Japan
Andes Technology Corp.
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RISC-V and Functional Safety
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Fabio Malatesta
Product Marketing Engineer
CAES Gaisler
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RISC-V in Space
The IP ecosystem around the RISC-V ISA is quickly growing and is complemented by a variegated software ecosystem. This will allow designers targeting space applications to re-use developments from other application fields and focus their efforts on a spects tied to the aerospace domain, in the form of fault tolerance and radiation hardening. ...
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Alexander Kozlov
CTO
CloudBEAR
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RISC-V processor IP product line
CloudBEAR processor IP portfolio will be presented from microcontroller cores to Linux out-of-order cores. Focus of talk will be about new features of CPU IP and new extensions support like cryptographic extensions, bitmanip, packed-simd. Example o f customer use cases will be presented. ...
Online Only
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Break
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4.30 pm
Security Solution
Chairperson: Bart Stevens - Rambus, Inc. ( About me) |
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Ranga Desikachari
Head of Engineering
Crypto Quantique
with Matt Douthwaite
Senior Analog IC Design Engineer
Crypto Quantique
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Overcoming Challenges in PUF Development
Overcoming Challenges in PUF Development: A physically unclonable function (PUF) is a device that can generate a unique random number that can provide the basis of a hardware root-of-trust to enhance the security of a device. What are the challen ges in developing PUF? What system considerations should be considered for a PUF to generate a secure cryptographic key? In this presentation, we describe the challenges which need to be overcome when developing PUFs, and we take a deep dive into lessons learned as we developed our 2nd generation quantum driven PUF, QDID. ...
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Ruud Derwig
Senior Principal Architect
Synopsys, Inc.
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Post-Quantum Cryptography: Theory to Accelerated Practice
Post-Quantum Cryptography (PQC) has received a fair amount of attention over the past few years, especially with the quantum threat becoming a closer reality. NIST's PQC standardization process is fully underway. Just recently, a significant mile stone of the path where the PQC algorithms are gradually becoming the cryptographic default was achieved – NIST has announced the first set of standardized PQC algorithms. For transition to PQC, there are various challenges to overcome in commercial solutions. Crypto agility is required in protocols and implementations such that today's algorithms can be seamlessly replaced with the PQC alternatives. Agility in software via firmware updates is much easier than agility in hardware. However, like today's algorithms, hardware acceleration and implementation are required for PQC to meet performance and security targets. ...
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Geert-Jan Schrijen
CTO
Intrinsic ID
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Building a Root of Trust with SRAM PUF and tRoot HSM
An embedded Hardware Security Module (HSM) is one of the strongest ways to implement secure authentication, trusted communication, and data protection on SoCs. Combining such an HSM with Physical Unclonable Function (PUF) technology adds an additiona l layer of protection by generating secure cryptographic keys from device-unique variations within the silicon of the chip itself. PUF technology enables reconstruction of a cryptographic root key every time the chip is powered up without storing any sensitive data in non-volatile memory, making it significantly harder for attackers to obtain key material and thereby substantially raising the level of security. We show how the Synopsys tRoot HSM is combined with Intrinsic ID's SRAM PUF technology to provide a complete security offering for modern SoCs. ...
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Ismail Guedira
Head of Sales EMEA
Secure-IC
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The importance of security lifecycle management
To ensure a fully managed and secure end-to-end cybersecurity solution, it is necessary to have full control over the product lifecycle and its security. A lifecycle management solution ensures at every stage of a product's life, from IC manufactu ring, to the field deployment and then the decommissioning of devices that include those ICs, that product security is maintained, and that each stakeholder only has access to the relevant functions and services at each step of the product's life. Especially for connected devices lifecycle management, a comprehensive chip to cloud solution that enables provisioning, device management, device monitoring and device identity management, and offers differentiated security services for chip manufacturers and users can bring high additional value to the products. ...
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6 pm
Have you visited all the booths ?
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7.30 pm
Wine tasting contest !!!
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8 pm
D&R 25th Anniversary Banquet !!!
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8.40 am
Chiplet and Die-to-Die Interface
Chairperson: Nicolas Gaude - Dolphin Design ( About me) |
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Letizia Giuliano
Vice President Solution Engineering
Alphawave Semi
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Chiplet and Die-to-Die Interface Interoperability - how to accelerate path to a real Open Ecosystem
Heterogeneous chiplet-based designs enable the integration of die from multiple process nodes and vendors into a single-package product. This emerging technology is needed to boost compute power while building cost-effective systems for High-Performa nce Computing (HPC), Artificial Intelligence (AI), and Machine-Learning System On Chip (ML SOC) products. In this paper, we introduce industry efforts to accelerate the chiplet ecosystem and the key metrics used to ensure design and technology interoperability between chiplet die coming from different sources. Today, most chiplet-based logic products are based on closed interfaces and integrate die from a single company, thereby creating silos of inter-company technical specifications, workflows, and business requirements. It is an obvious choice for the industry to demand more with regards to chiplet integration and have reason to accelerate its adoption. Efforts to build an ecosystem for chiplets have been materialized through the standardization of Die-to-Die (D2D) IP subsystem interfaces for plug-in solutions (thereby addressing interoperability at different levels) by the Open Domain-Specific Architecture (ODSA) Working Group, the Optical Internetworking Forum (OIF), and most recently, the Universal Chiplet Interconnect Express™ (UCIe™) . The chiplet industry has placed more emphasis on the newer UCIe specification due to its completeness on what is required for an open D2D interface; this translates into new opportunities—as well as challenges—in testing standards compliance for multi-chiplet products. The opportunity to leverage established protocol interfaces and practices readily available by product designers means that those currently integrating interfaces, such as PCIe and CXL protocols, can simply reuse proven methodologies. While the challenge in enabling a high degree of interoperability using standard defined form factors and test structures when integrating different chiplets across multiple vendors is not to be underestimated, this enablement of interface/practice democratization on the concept of chiplet product will be invaluable. This paper reviews recent developments in chiplet interoperability metrics (including protocol layer definitions and physical interfaces) by leveraging current industry work on PCIe and CXL protocols and High-Bandwidth Memory (HBM) interfaces. This paper also discusses the extension of chiplets to test products based on open D2D interfaces. After defining the path towards protocol and electrical interface compliance, product designers will then have to address packaging and test challenges that will be inherent when integrating chiplets from multiple vendors. Thus, this paper further discusses how the work in HBM interfaces and Design For Test (DFT) scan standards for ‘system-in-package’ devices can be extended to heterogenous chiplet-based products. ...
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Andreas Vielhaber
Sr. Staff Application Engineer
Synopsys, Inc.
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Strength of UCIe for Multi-Die Systems
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9.20 am
Low Power Design
Chairperson: Nicolas Gaude - Dolphin Design ( About me) |
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Ken Potts
COO
Alphacore, Inc.
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FDSOI High speed, low power hybrid ADC's for Communications, AI, and Automotive applications
Alphacore has continued to expand the FDSOI offering at GF22FDX. In this presentation we will update the audience on new additions to our product line currently being integrated into Communications, AI, Automotive, and Quantum Compute applications.
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Michal Staworko
co-founder
Phonemic
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Lowering the power consumption of voice-controlled IoT devices
Contribution describes: - short summary of use of voice interfaces in IoT devices and applications - pros and cons of different approaches to voice recognition (cloud, edge) - impact of power and resource consumption of voice interfaces on SoC - concept of Voice Activity Detection for lowering power consumption - different approaches in scientific literature and industry solutions to Voice Activity Detection - advantages of Phonemic's VAD IP-Core in lowering the system power consumption ...
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Break
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10.25 am
Memory and Analog IP
Chairperson: Erkan Isa - Fraunhofer-Gesellschaft ( About me) |
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Eran Briman
VP Marketing & Business Development
Weebit Nano
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How Embedded Non-Volatile Memory IP Can be a Differentiator
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Graham Woods
Director, Field Application Engineering Group
Agile Analog
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Analog IP, the way you want it
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Vincent Bligny
CEO
Aniah
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All you need is an Electrical Rule Checker !
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Julian Jenkins
CTO and CEO
Perceptia Devices
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Selecting the Correct PLL for Your Application
PLLs are built to support a wide range of applications, including RF systems, high performance computing, IoT and embedded applications and clocking ADCs and DACs. This talk will discuss the differences between the requirements of the different appli cations and help you to establish what PLL specifications are important in your system. ...
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11.45 am
Ethernet IP
Chairperson: Nikos Zervas - CAST, Inc.
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Flemming Kongsfelt
Manager Packaged IP Solutions
Comcores
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Deterministic transmission of time critical information with TSN Ethernet (Time Sensitive Network)
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Andreas Emeretlis
Hardware Design Engineer
CAST, Inc.
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Addressing performance challenges of TCP/IP stack implementations
The offloading of TCP/IP in hardware is a popular option for addressing the reliable and low-latency requirements of modern high-speed networks. This protocol offers a connection-oriented communication that guarantees the data delivery through data a cknowledgments and retransmissions, while also implementing flow control and congestion control mechanisms. The performance of the implementation depends not only on the design itself but also on the included protocol features that allow efficient operation in different network environments and different peers. In unreliable or highly congested networks, where packet loss is very common, the implementation of congestion control methods is crucial to avoid overwhelming the network while maintaining an equilibrium between conservative behavior and aggressive claiming of additional bandwidth. In addition, different transmit and receive policies affect the network performance since the transmission of small data packets and acknowledments consumes the bandwidth, whereas sending larger packets is generally more efficient. Finally, the TCP protocol is tightly coupled with other network protocols, the integration of whom in a single solution can provide seamless communication for a higher-layer application over the network. The TCPIP-1G/10G core from CAST implements a complete TCP/IP Hardware Protocol Stack, which opens, maintains, and closes TCP connections. The system integrating the TCPIP-1G/10G core can configure network parameters and preferences by accessing its control registers, and the core is then able to receive and send data via streaming data interfaces. The highly configurable core can adapt to different applications and diverse system requirements while offering low-latency communication and considering the performance of the network. ...
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12.30 pm
Enjoy your Lunch Break, sit down with your client and rest in "Le Jardin"
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1.30 pm
Video & Imaging IP
Chairperson: Nikos Zervas - CAST, Inc.
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Mahmoud Banna
General Manager
Mixel, Inc.
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Leveraging MIPI DSI-2 & MIPI CSI-2 Low-Power Display and Camera FPGA-based Subsystems
This presentation looks at how MIPI D-PHY℠, MIPI CSI-2® and MIPI DSI-2℠ specifications were implemented on an FPGA IC supporting a wide range of applications for smart phones, tablets, wearables, VR headsets and other devices. It also cov ers a real-life use case in a highly configurable FPGA solution from Hercules Microsystems. ...
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Dr. Slava Chesnokov
CTO
Lemur-Imaging Ltd.
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Ultra-compact image compression IP core for saving on chip SRAM
Lemur Imaging have developed an ultra compact image compression core, LMR, that can deliver perceptually lossless 2x compression with no impact to image quality. The LMR CODEC is the smallest visually lossless CODEC in the industry, with a gate cou nt equivalent to 500 pixels. The core can be used for saving silicon area for any line memory which is longer than 1k pixels. For 4K+ imaging subsystems the area saving and corresponding power saving, when using LMR is significant. This is increasingly important for sub 10nm designs, as memory no longer scales at the same rate as logic, at these process nodes. LMR IP can be used in convolution blocks, scalers and other filters used in camera and display pipelines. In addition LMR IP can be used to reduce the size of memory in Computer Vision accelerators, line/tile memory in GPU’s and line buffers in SLAM accelerators. With the emerging AR/VR headset market, the need to reduce power by replacing DRAM with on chip SRAM is becoming paramount. LMR IP can reduce this SRAM area by 50% so helping to reduce cost and power. ...
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2.10 pm
IP based SoC Design
Chairperson: Pascal Vivet - CEA ( About me) |
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Chouki Aktouf
CEO/CTO
Defacto Technologies
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Unified methodology for SoC design assembly including logic, power and timing constraints
Defacto's presentation will focus on a unified methodology to build complex SoCs at the front-end by managing jointly several dimensions including logic, power intent and timing constraints. Such methodology is made possible thanks to unified dat a structure were an SoC is described by capturing simultaneously information given RTL description, UPF description, SDC description, etc. with open APIs to let designers extract information from such data structure and update them. Unified design assembly means having the same level of automation when managing the SoC logic, the power intent, the timing constraints, etc.. During the assembly process, designers expect ease insertion of internal and third party IPS and promoting design information (RTL, IPXACT, UPF, SDC, ..) to the top level. Such a methodology also requires an underlining checking capabilities like coherency between different design files. To make such methodology real, advanced EDA tools and platforms are needed. ...
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Ilya Temnikov
Director of EDA Engineering
Thalia
with Jean-Francois Lambert
Director of Business Development
Thalia
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Tackling ROIC SoC Design Reuse challenges with AMALIA platform
A high-quality image processing IC design company needed to reuse their readout IC from 350 nm to 180 nm. Thalia's using its AMALIA reuse platform alongside expertise delivered a cost effective and efficient solution to the customer. The platform allowed Thalia and the customer to analyse and estimate the impact of the new technology on both design, performance and to minimize any impact on the system development schedule. A successful IP migration and thorough analysis of the target process means the customer was able to cost-effectively extend the product's lifeline and avoid End of Life decisions. ...
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Dan Alexandrescu
Core Team Leader
Synopsys, Inc.
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Essential IP for the Enablement of Silicon Lifecycle Management
Silicon Lifecycle Management (SLM) is gaining momentum within the industry and makes product development and deployment more deterministic by enabling greater levels of observability into silicon health. Using embedded monitors as well as existing te st infrastructure allows real time, meaningful data to gathered at every phase of the device lifecycle, this data is then transported off chip and stored in a unified SLM database ready to be analysed. Based on this analysis, insightful decisions can be made and the correct action taken. This foundation of enriched in-chip observability, analytics, and integrated automation, enables improved silicon health. In-chip environmental monitors provide real time data on dynamic conditions like process variability, voltage supply and thermal activity. Structural monitors enable the measurement of timing margins of real functional paths. Alongside the embedded monitors, high speed access and test IP provides adaptive high bandwidth testing over a functional interface, reducing test time and cost with a lower pin count, enabling testing through entire silicon lifecycle. This presentation will explain the importance of these essential IPs in enabling effective management of the silicon lifecycle from In-Design, In-production, In-Ramp and ultimately In-Field operation, as well as exploring some specific use cases. ...
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Yoan Dupret
CTO and Managing Director
Menta
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Programmable logic for ASIC/SoC without pain
The combination of edge computing, highly parallel always evolving algorithms and increasing design costs is leading to a strong requirement of adaptive computing acceleration - which is best served by integrating programmable logic, in the form of e mbedded FPGA IPs. However, integrating an eFPGA IP is often seen as a complexed, costly, risky and long process - in one word: painful. In this talk, we will explain how Menta is offering the way to integrate programmable logic without pain. ...
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3.30 pm
Open Forum
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Abdelgader Abdalla
Senior Researcher
Instituto de Telecomunicações
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A Deep Learning-based Surrogate Model and Automata Synthesis Convergence For Jitter and Eye Estimation in Nonlinear High-Speed Links
This work proposed a fast hybrid short transient simulation assumption method based on the Barycentric Lagrange chaos surrogate model and automata synthesis convergence to estimate Jitter parameters, and built an eye diagram over high-speed SerDes ch annel systems. To the best of our knowledge, this is the first time that a hybrid methodology that uses finite automata to guide a deep machine learning-based surrogate model has been proposed for eye diagram synthesis and jitter parameters estimation at the receiver. The proposed Barycentric Lagrange chaos has reduced the computational cost from O(n2) to O(n) in contrast to legacy state of the arts transient simulation and polynomial chaos (PC) model-based surrogate model. Moreover, integrated finite automata within the proposed machine learning method have reduced computationally expensive eye diagram synthesis steps inherent in the current state of the arts mentioned above. The proposed technique shows excellent synthesis, accuracy and less simulation runtime compared to the traditional transient analysis simulation and PC method. ...
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4 pm
Event closure !!! Lucky Draw !!!
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