The 100G AES Encryption Core is a high performance and yet low footprint AES engine for 100G/s application. Typical applications are providing bulk encryption for 100GE, LO ODUCn and OTU4.

Rambus Crypto Accelerator 3DES-ECB Hardware Cores offload compute intensive cryptographic algorithms in SoC s CPU at 100x performance (when run at identical frequencies) and 10% of the power consumpti...

Attacks against digital circuits can be performed by directly tampering with the device s internal structure. These attacks are intrusive, and regroup attempts to directly probe or force signals, remo...

Rambus Crypto Accelerator AES-AE-Fast Hardware Cores offload compute intensive cryptographic algorithms in SoC s CPU at 100x performance (when run at identical frequencies) and 10% of the power consum...

Rambus DPA Resistant AES-FBC Cryptographic Accelerator Cores offload compute intensive cryptographic algorithms in SoC s CPU at 100x performance (when run at identical frequencies) and 10% of the powe...

The EIP-39 AES Accelerators implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS) Publication 197. The accelerators include I/O reg...

The EIP-36 AES Engines implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS) Publication 197. The accelerators include I/O register...

The EIP-38 - AES/GCM/XTS/LRW Engines are specifically suited for next generation processors deployed in networking and storage appliances that need to support combinations of AES (with its regular fee...

The EIP-37 is the IP for accelerating the AES Key Wrap cipher algorithm (NIST-Key-Wrap & RFC3394). Designed for fast integration, low gate count and full transforms, the EP-37 accelerator provides a r...

Rambus DPA & Fault Injection Resistant AES-ECB Cryptographic Cores prevent against the leakage of secret cryptographic key material through attacks when integrated into an SoC or FPGA. AES-ECB 1 billi...

Rambus Crypto Accelerator AES-AE–Fast Hardware Cores offload compute intensive cryptographic algorithms in SoC’s CPU at 100x performance (when run at identical frequencies) and 10% of the power consum...

Rambus DPA & Fault Injection Resistant AES-AE Cryptographic Cores prevent against the leakage of secret cryptographic key material through attacks when integrated into an SoC or FPGA. AES-AE 1 Billion...

Rambus Crypto Accelerator AES-AE–Fast Hardware Cores offload compute intensive cryptographic algorithms in SoC’s CPU at 100x performance (when run at identical frequencies) and 10% of the power consum...

The EIP-61 is the IP for accelerating AES-GCM based cryptographic solutions. Designed for easy integration and very high performance the EIP-61 crypto accelerator provide a reliable and cost-effective...

The AES-GCM Ultra-low latency crypto engine is targeted for CXL link encryption with an implementation of the AES-GCM algorithm compliant with the NIST SP 800-38D standard. The unique architecture ena...

The Anti Row-Hammer IP takes part in Memory Controller in order to protect the Memory against Rowhammer Attacks, especially on RAM. This IP is able to determine if the number of access requests to a M...

The EIP-44 is the IP for accelerating the ARC4 stream cipher algorithm (used for legacy SSL & IPsec).

The ARIA crypto engine includes a generic implementation of the ARIA algorithm which is the block cipher standard of South Korea.

The EIP-11 ARIA algorithm, as specified in RFC 5794. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling and GHASH. Besides the...

The BA452 is a secure connection engine that can be used to off-load the compute intensive Public Key operations.

The eSecure IP is a single subsystem for RISC-V based SoC to address key security challenges, playing the role of root-of-trust.

The EIP-32 AES Engines implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS) Publication 197. The accelerators include I/O register...

Our solution is a secure public key infrastructure engine that can be used to offload compute-intensive public key operations such as signature generations and verifications.

The Boot Protection Pack is a solution provided by Secure-IC to ensure a Secure Boot function. The Boot Protection Pack provides a secure root-of-trust with a high level of resistance against malevole...

The Camellia Engine implements the Camellia crypto algorithm, as specified in Specification of Camellia and RFC3713.

The Secure-IC s CamoGate IP has for goal to protect a circuit against reverse-engineering. Reverse engineering of an Integrated Circuit is a process which aims at identifying its structure, design and...

Rambus DPA Resistant Hardware Cores prevent against the leakage of secret cryptographic key material through attacks when integrated into an SoC or FPGA. ChaCha 20 Fast DPA resistant cryptographic acc...

The EIP-13 ChaCha engine implements the ChaCha20 algorithm, as specified by [ChaCha]. The accelerators include I/O registers and an encryption/decryption core. Designed for fast integration, low gate ...

Chacha20-Poly1305 high performance IP core for authenticated encryption.

Rambus Circuit Camouflage Technology (formerly Inside Secure), also known as SecureMedia Library (SML), is an anti-reverse engineering and anti-cloning protection for integrated circuits that has both...

Inside Secure Circuit Camouflage Technology, also known as SecureMedia Library (SML), is an anti-reverse engineering and anti-cloning protection for integrated circuits that has both Commercial and Government Applications.

Inside Secure s Code Protection technology provides powerful automated software protection tools applicable across Mobile, IoT, Desktop and Server platforms.

Multimedia consumers expect easy and convenient access to the latest movies and TV shows wherever they are. Inside Secure enables content and service providers to securely deliver premium content to virtually any connected device the way users want it, online or offline, for use cases like video-on-demand, live and catch-up TV.

Inside Secure Content Protection Server is a fifth generation, interoperable, server-side Digital Rights Management (DRM) solution. Designed for wireless and wireline operators and service providers, Content Protection Server implements and extends multiple DRM technologies such as Microsoft PlayReady and Google Widevine DRM while providing common integration interfaces.

The Cryptographic Coprocessor (or CryptoSoc Accelerator) is a hardware IP core platform that accelerates cryptographic operations in System-on-Chip (SoC) environment on FPGA (Intel SoC, Xilinx Zynq) and ASIC.

The Arm CryptoCell-300 family of embedded security solutions serves high-efficiency systems with a small footprint and low power consumption.

Providing superior security and tamper resistance, while being highly-cost effective. Our cores complement existing security implementations, and are ideal for preventing counterfeiting in a broad number of applications.