The Arm CoreLink DMA-350 direct memory access (DMA) controller offloads memory movement tasks from the CPU to improve system performance and energy-efficiency. It includes support for scatter gather, ...

The CoreLink SSE-200 subsystem is the foundation on which SoC designers will build a new generation of secure IoT products.

Low power designs are very critical to mobile and IoT applications. M31 low power solution is comprehensive for low power designs.

For designs requiring high performance with multiple data channels and perhaps multi-processing, we can build your subsystem around the Cortex-A5 processor.

Supports Cortex-M3/M4 (or equivalent) processor | Power Management Unit | AMBA (AHB) | AHB Multi-matrix bus infrastructure | External Nor Flash controller | DMA (single or multi-channel) | Internal SRAM controller | Interrupt Controller (optional) | QSPI with Execute in Place (XIP) for standard Flash parts such as Winbond and Spansion | AHB/APB bridge | Standard APB Peripheral package | I2C, SPI, UART, GPIO, Timers, Watchdog

Supports Cortex-M3/M4 (or equivalent) processor | Power Management Unit | AMBA (AHB) | AHB Multi-matrix bus infrastructure | External Nor Flash controller | DMA (single or multi-channel) | Internal SRAM controller | Interrupt Controller (optional) | QSPI with Execute in Place (XIP) for standard Flash parts such as Winbond and Spansion

The subsystem is specifically designed for Cortex A5(or equivalent) based processor applications that target complex devices that need both higher performance and perhaps multiprocessing.